Method of implant verification in semiconductor device using ret

Details Method of implant verification in semiconductor device using ret Method of implant verification in semiconductor device using ret

1996-09-13

1998-01-06

Dutton, Brian

Fishing, trapping, and vermin destroying

437 20, H01L 21265, H01L 2166, G01R 3126

Patent

active

057054045

ABSTRACT:
A semiconductor device and method of making same which includes a semiconductor substrate having a moat region with an ion implant in the moat region and a window in the substrate spaced from the moat region, electrically decoupled therefrom and having an ion implant therein in the form of a predetermined pattern. The moat region can contain one or more active and/or passive components therein. The method of fabrication comprises providing a semiconductor wafer, forming a moat region and an associated window region on the wafer, forming at least portions of electrical devices in the moat region by implanting ions therein, forming a predetermined non-electrical component pattern in the window by implanting ions in the window concurrently with the implanting of ions in the moat and completing fabrication of at least one electrical component in the moat region. Implants are verified by the above described device and selectively etching the window with an etchant selective to one of the substrate with ion implant therein and the substrate without ion implant therein to provide the pattern at a different level from the remainder of the window. The pattern is a non-electrical component pattern and the etchant is preferably selective to the portion of the window with ion implant to cause the pattern to lie below the portion of the window without ion implant.

REFERENCES:
patent: 5051374 (1991-09-01), Kagawa et al.
patent: 5106764 (1992-04-01), Harriott et al.
patent: 5403753 (1995-04-01), Huber et al.

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