Method of identifying floorplan problems in an integrated...

Details Method of identifying floorplan problems in an integrated... Method of identifying floorplan problems in an integrated...

2007-08-28

2007-08-28

Whitmore, Stacy A (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

11079998

ABSTRACT:
A method and apparatus are provided for identifying a potential floorplan problem in an integrated circuit layout pattern. The method and apparatus identify a critical timing path in the layout pattern and identify a start point and one or more end points along the timing path. It is then determined whether any of the one or more end points are floor-planned objects. For each end point that is a floor-planned object, the method and apparatus compare a distance between that end point and the start point with a distance threshold to produce a comparison result. A potential floorplan problem can be identified if the distance exceeds the distance threshold.

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