Optics: measuring and testing – Of light reflection
Reexamination Certificate
2001-04-06
2003-09-09
Nguyen, Tu T. (Department: 2877)
Optics: measuring and testing
Of light reflection
Reexamination Certificate
active
06618149
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to a method of identifying film stacks based upon optical properties, and a system for accomplishing same.
2. Description of the Related Art
By way of background, modern integrated circuit devices, e.g., microprocessors, ASICs, memory devices, etc., are comprised of millions of field effect transistors formed on a semiconducting substrate, such as silicon. The substrate may be doped with either N-type or P-type dopant materials. An illustrative field effect transistor
10
, as shown in
FIG. 1
, may have a doped polycrystalline silicon (polysilicon) gate electrode
14
formed above a gate insulation layer
16
. The gate electrode
14
and the gate insulation layer
16
may be separated from doped source/drain regions
22
of the transistor
10
by a dielectric sidewall spacer
20
. The source/drain regions
22
for the transistor
10
may be formed by performing one or more ion implantation processes to introduce dopant atoms, e.g., arsenic or phosphorous for NMOS devices, boron for PMOS devices, into the substrate
11
. Shallow trench isolation regions
18
may be provided to isolate the transistor
10
electrically from neighboring semiconductor devices, such as other transistors (not shown).
The gate electrode
14
has a critical dimension
12
, i.e., the width of the gate electrode
14
, that approximately corresponds to the channel length
13
of the device when the transistor
10
is operational. Of course, the critical dimension
12
of the gate electrode
14
is but one example of a feature that must be formed very accurately in modern semiconductor manufacturing operations. Other examples include, but are not limited to, conductive lines, openings in insulating layers to allow subsequent formation of a conductive interconnection, i.e., a conductive line or contact, therein, etc.
In general, semiconductor manufacturing operations involve, among other things, the formation of layers of various materials, e.g., polysilicon, insulating materials, etc., and the selective removal of portions of those layers by performing known photolithographic and etching techniques. These processes are continued until such time as the integrated circuit device is complete. Additionally, although not depicted in
FIG. 1
, a typical integrated circuit device is comprised of a plurality of conductive interconnections, such as conductive lines and conductive contacts or vias, positioned in multiple layers of insulating material formed above the substrate. These conductive interconnections allow electrical signals to propagate between the transistors formed above the substrate.
The precise combination of steps used in manufacturing integrated circuit devices, e.g, so-called process flows, may change over time as technological advances and/or equipment improvements occur. In some cases, multiple layers of material are formed to define a film stack from which various features of a transistor may be formed. For example, in forming gate electrodes for transistor devices, one process flow might involve the formation of a layer of silicon dioxide (which will ultimately become the gate insulation layer
16
) that is grown in a dry furnace process, a doped layer of polysilicon (which will ultimately become the gate electrode
14
), and an anti-reflecting coating (ARC) layer comprised of silicon nitride. These layers will ultimately be subjected to one or more processing operations, e.g., etching, to define various components of the transistor, e.g., the layer of polysilicon may be patterned to define the gate electrode
14
. Subsequent improvements in materials, manufacturing techniques and/or design may lead to changes in the process flows used to make such transistors. For example, in another process flow, the polysilicon layer from which the gate electrodes will be formed may be changed such that it is comprised of an undoped polysilicon, and the ARC layer may be changed to silicon oxynitride. Moreover, the thickness of the various layers of the film stack may vary from one process flow to another.
Unfortunately, several process flows may be in use in a given fabrication facility at any one time. That is, film stacks on which processing operations are to be performed, e.g., etching, may be comprised of different layers of materials having differing thicknesses. Such a situation occurs because, in most fabrication facilities, a new process flow is not implemented throughout the entire facility in a wholesale fashion. Given that preexisting process flows produce devices of acceptable quality, production managers are, understandably, reluctant to make wholesale changes in the manufacturing operation, despite the fact that a new process flow may have been extensively tested prior to its introduction into a manufacturing environment. Typically, such new process flows tend to gradually be introduced and used until such time as later developed, improved process flows are introduced.
As a result, there may be several different film stacks being produced in the fabrication facility at any given time. Unfortunately, these variations may lead to problems in the manufacturing of integrated circuits. For example, in an extreme case, an etching process may be performed on what is assumed to be a film stack comprised of a layer of polysilicon and a layer of silicon nitride, when, in fact, the film stack is comprised of a layer of polysilicon and a layer of silicon oxynitride. If such an event were to occur, then the etching process may render the resulting product unusable or at least cause extensive rework to be performed. Such problems result in expensive delays, cost overruns, and a general decrease in the yield of semiconductor manufacturing operations.
The present invention is directed to a method and system that may solve, or at least reduce, some or all of the aforementioned problems.
SUMMARY OF THE INVENTION
The present invention is generally directed to a method of identifying film stacks based upon optical properties, and a system for accomplishing same. In one illustrative embodiment, the method comprises determining the composition of a film stack by providing a library of optical characteristic traces, each of which correspond to a film stack combination, providing a wafer having a film stack formed thereabove, and illuminating the film stack. The method further comprises measuring light reflected off the film stack to generate an optical characteristic trace for the film stack, and determining the composition of the film stack formed above the wafer by correlating or matching the generated optical characteristic trace for the film stack above the wafer to an optical characteristic trace from the library, the optical characteristic trace from the library having an associated film stack composition comprised of a plurality of known process layers.
In another illustrative embodiment, the method comprises determining the composition of a film stack by providing a library of optical characteristic traces, each of which correspond to a film stack combination comprised of a known combination of process layers formed above a known grating structure, providing a wafer having a film stack formed above said known grating structure, and illuminating the film stack and the known grating structure. The method further comprises measuring light reflected off the film stack and the known grating structure to generate an optical characteristic trace for the film stack and the known grating structure, and determining the composition of the film stack formed above the wafer by correlating or matching the generated optical characteristic trace for the film stack and the known grating structure to an optical characteristic trace from the library, the optical characteristic trace from the library having an associated film stack combination comprised of a plurality of known process layers formed above said known grating structure.
REFERENCES:
patent: 4625114 (1986-11-01)
Nguyen Tu T.
Williams Morgan & Amerson P.C.
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