Method of hydrogen anneal to a semiconductor substrate

Details Method of hydrogen anneal to a semiconductor substrate Method of hydrogen anneal to a semiconductor substrate

1999-12-07

2002-01-01

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S770000

Reexamination Certificate

active

06335278

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a method of forming a semiconductor device such as a semiconductor integrated circuit, and more particularly to a method of hydrogen annealing a semiconductor substrate for forming a semiconductor device such as a semiconductor integrated circuit in order to improve device performance and reliability.
To form semiconductor integrated circuits such as memory and logic circuits, various devices are formed on a substrate and then an inter-layer insulator is formed over the substrate, before the substrate is subjected to a hydrogen anneal in a hydrogen-nitrogen atmosphere at a temperature of 400° C.
This hydrogen anneal is effective for improvements in characteristics of electrical connections between metal interconnections and also characteristics of electrical connections between a semiconductor substrate and a metal interconnection. The hydrogen anneal is also effective for improvements in performances and reliability of the semiconductor device and an improvement in yield of the semiconductor device.
In case of dynamic random access memory, interface states are present on an interface of silicon substrate and a silicon oxide film such as a field oxide film and a gate oxide film. A leakage of current from a diffusion layer through this interface state to the substrate is caused, whereby a hold characteristic of the DRAM is deteriorated. The interface state also causes variation in characteristics of the device such as transistors, for example, variations in a threshold voltage and a current-voltage characteristic from designed values. This interface state makes it difficult to improve the yield and reliability of the semiconductor device. The hydrogen anneal is effective to obtain desired characteristics of the transistors such as threshold voltage and current-voltage characteristic for other semiconductor devices than the DRAM, for example, logic devices. The interface states are caused by dangling bond of silicon near the interface between silicon and silicon interface. The hydrogen anneal supplies hydrogen to the interface between silicon oxide so that the dangling bond is terminated with hydrogen supplied, whereby the interface state is reduced.
In recent years, scaling down and increase in density of integration of the semiconductor integrated circuits have been on the increase. Further, a multilayer structure has been on development. Furthermore, new multilayer structures, electrode materials, interconnection materials and insulator materials have been developed and used. These new conditions make it difficult to penetrate and diffuse hydrogen to the interface between silicon and silicon oxide through the hydrogen anneal. In order to solve this difficulty, it is necessary to make an anneal time longer and to rise an anneal temperature. If the anneal time becomes longer, then a problem with reduction in productivity of the semiconductor device is raised. If the anneal temperature is risen, spikes or hillocks are caused on metal interconnection such as an aluminum interconnection, whereby the reliability is deteriorated. Furthermore, the temperature increase does not necessarily cause desired effects of the hydrogen anneal.
The permeability of hydrogen depends upon materials of the device. For example, permeability of hydrogen to silicon oxide films such as the inter-layer insulator and the field oxide film are relatively high. A permeability of silicon nitride film which may often be used as an etching stopper and a dielectric film of a capacitor as well as a contamination control film is low. Particularly, a silicon nitride film deposited by a low pressure chemical vapor deposition method has a high film density, for which reason the silicon nitride film serves as a diffusion barrier to diffusion of hydrogen.
Metal materials such as aluminum for metal interconnections absorb hydrogen. Barrier material materials such as Ti and TiN also absorb hydrogen. Further, polysilicon used for interconnection and electrodes also absorb hydrogen. Namely, hydrogen is absorbed into the metal interconnection materials, the barrier metal materials, and polysilicon whereby the diffusion rate is remarkable reduced until the absorption is saturated to allow hydrogen to permeate those materials.
On the other hand, it is possible to consider that hydrogen penetrates from a bottom of a substrate. However, in recent years, a wafer diameter has been on the increase whereby a thickness of the wafer has also been on the increase. For example, 6-inch wafer has a thickness of 675 micrometers. 8-inch wafer has a thickness of 725 micrometers. 12-inch wafer has a thickness of over 770 micrometers. The increase in thickness of the wafer means that the necessary diffusion depth is increased, thereby making it difficult to penetrate hydrogen from the substrate bottom surface to the interface between silicon and silicon oxide. Further, when a polysilicon film and a silicon nitride film which serve as diffusion barriers to hydrogen are formed, those films are also formed or adhered on the bottom surface of the substrate, whereby it is no longer possible that hydrogen is diffused from the bottom surface of the substrate to the interface between silicon and silicon oxide. Furthermore, in case, a polysilicon film which serves as the diffusion barrier to hydrogen is formed on the bottom surface of the substrate for extrinsic gettering, whereby it is also no longer possible that hydrogen is diffused from the bottom surface of the substrate to the interface between silicon and silicon oxide. Moreover, the deep diffusion depth from the bottom surface of the substrate needs a high temperature hydrogen anneal.
The difficulty in application of the hydrogen anneal to the advanced semiconductor devices will be described with reference to the drawings.
FIG. 1A
is a fragmentary plan view illustrative of a stacked DRAM.
FIG. 1B
is a fragmentary cross sectional elevation view illustrative of a stacked DRAM taken along a B—B line of FIG.
1
A.
FIG. 1C
is a fragmentary cross sectional elevation view illustrative of a stacked DRAM taken along a C—C line of FIG.
1
A. Field oxide films
2
are selectively formed on a surface of a p-type silicon substrate
1
which has a predetermined crystal orientation. Silicon nitride films
6
are formed over the field oxide films
2
. Diffusion layers
5
are selectively formed in an active region of the silicon substrate
1
defined by the field oxide film
2
. Gate oxide films
4
of silicon oxide are formed on the active region of the silicon substrate
1
. Gate electrodes
3
are formed on the gate oxide films
4
. Each gate of the electrodes
3
comprises laminations of a n-type polysilicon film and a tungsten silicide film which are not illustrated. The diffusion layers
5
are self-aligned to the gate electrodes
3
and the field oxide films
2
. Silicon nitride films
6
are formed on side walls of the gate electrodes
3
. n-type polysilicon pads
9
are formed on the diffusion layers
5
and between the side wall silicon nitride films
6
. The n-type polysilicon pads
9
are formed by an anisotropic selective epitaxial growth. A silicon oxide interlayer insulator
7
is formed over the gate electrodes
3
, the side wall silicon nitride films
6
. Contact holes are formed in the silicon oxide inter-layer insulator
7
, so that the contact holes are positioned just over the n-type polysilicon pads
9
. n-type polysilicon contacts
8
are filled within the contact holes so that the n-type polysilicon contacts
8
are made into contact with the n-type polysilicon pads
9
, whereby the n-type polysilicon contacts
8
are electrically connected through the n-type polysilicon pads
9
to the diffusion layers
5
. Capacitive bottom electrodes
10
are selectively formed over the silicon oxide inter-layer insulator
7
, so that the capacitive bottom electrodes
10
are made into contact with the n-type polysilicon contacts
8
, whereby the capacitive bottom electrodes
10
are electrically connected through the n-type polysi

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