Method of high-performance CMOS design

Details Method of high-performance CMOS design Method of high-performance CMOS design

2000-09-14

2003-04-15

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S112000, C326S096000

Reexamination Certificate

active

06549038

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates to complementary metal oxide semiconductor (CMOS) logic, and more particularly, to a design method for increasing the speed of the CMOS logic using output prediction techniques.
BACKGROUND OF THE INVENTION
CMOS circuitry is commonly used to implement logic functions, such as NOR and NAND gates. Traditionally, such CMOS logic gates have been constructed by the interconnection of transistors whose terminals are connected to the inputs of the gates. For complex CMOS logic circuits, the digital signals must oftentimes propagate through several levels of gates before finally providing an output signal. These “static” CMOS logic circuits have been favored because of their high noise immunity and easy technology mapping. One major disadvantage of such static circuits, however, has been their relatively slow speed.
Dynamic CMOS logic was developed to allow increased speed. Dynamic CMOS logic circuits perform combinational functions using a clock signal. One type of dynamic CMOS logic is known as domino logic. Domino CMOS logic is commonly used in high-performance microprocessors for obtaining timing goals that are not possible using static CMOS logic. See e.g. “A New Family of Semi-Dynamic and Dynamic Flip-Flops with Embedded Logic for UltraSPARC-III,” F. Klass et al., IEEE J. Solid State Circuits, Vol. 34, No. 5, pp. 712-717 (May 1999); “Clock Delayed Domino for Adder and Random Logic Design,” G. Yee et al., Proc. IEEE Int'l Conf. on Computer Design (ICCD) (October 1996).
The increased performance of domino logic is due to reduced input capacitance, lower switching thresholds, and circuit implementations that typically use fewer levels of logic due to the use of efficient and wide complex gates. Dynamic CMOS logic can be used to realize an average speed improvement of about 60% over static CMOS logic for random logic blocks.
However, dynamic CMOS logic circuits have notable disadvantages. In the case of domino CMOS logic, logic must be mapped to a unate network, which usually requires duplication of logic. Perhaps the main disadvantage is the increased noise sensitivity compared to static CMOS logic.


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