Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2011-04-05
2011-04-05
Richards, N Drew (Department: 2895)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S003000, C438S614000, C438S618000, C438S620000, C438S674000, C257SE21665
Reexamination Certificate
active
07919407
ABSTRACT:
Described herein are novel, cost effective and scalable methods for integrating a CMOS level with a memory cell level to form a field induced MRAM device. The memory portion of the device includes N parallel word lines, which may be clad, overlaid by M parallel bit lines orthogonal to the word lines and individual patterned memory cells formed on previously patterned electrodes at the N×M intersections of the two sets of lines. The memory portion is integrated with a CMOS level and the connection between levels is facilitated by the formation of interconnecting vias between the N×M electrodes and corresponding pads in the CMOS level and by word line connection pads in the memory device level and corresponding metal pads in the CMOS level. Of particular importance are process steps that replace single damascene formations by dual damascene formations, different process steps for the formation of clad and unclad word lines and the formation of patterned electrodes for the memory cells prior to the patterning of the cells themselves.
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Kan Wai-Ming Johnson
Liu Daniel
Torng Chyu-Jiuh
Zhong Adam
Zhong Tom
Ackerman Stephen B.
Lee Kyoung
MagIC Technologies, Inc.
Richards N Drew
Saile Ackerman LLC
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