Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Patent
1998-01-13
2000-02-22
Lee, Thomas C.
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
710 55, 711212, 711220, 712220, 709213, G06F 1314, G06F 15163
Patent
active
060292121
ABSTRACT:
A system and method of accessing a memory location within a system having a processor and a plurality of memory locations separate from the processor. The system includes a plurality of external registers which are connected to the processor over a data bus, address translation means, connected to the processor over the data bus and an address bus, for calculating, based on an index written to the data bus, an address associated with one of the memory locations, and transfer means, connected to the plurality of external registers, for transferring data between the addressed memory location and one of the external registers.
REFERENCES:
patent: Re28577 (1975-10-01), Schmidt
patent: 4771391 (1988-09-01), Blasbalg
patent: 4868818 (1989-09-01), Madan et al.
patent: 4933933 (1990-06-01), Dally et al.
patent: 4974143 (1990-11-01), Yamada
patent: 4987537 (1991-01-01), Kawata
patent: 5008882 (1991-04-01), Kawata
patent: 5031211 (1991-07-01), Nagai et al.
patent: 5105424 (1992-04-01), Flaig et al.
patent: 5157692 (1992-10-01), Horie et al.
patent: 5170482 (1992-12-01), Shu et al.
patent: 5175733 (1992-12-01), Nugent
patent: 5218601 (1993-06-01), Chujo et al.
patent: 5218676 (1993-06-01), Ben-ayed et al.
patent: 5239545 (1993-08-01), Buchholz
patent: 5255376 (1993-10-01), Frank
patent: 5280474 (1994-01-01), Nickolls et al.
patent: 5313628 (1994-05-01), Mendelsohn et al.
patent: 5313645 (1994-05-01), Rolfe
patent: 5331631 (1994-07-01), Teraslinna
patent: 5333279 (1994-07-01), Dunning
patent: 5341504 (1994-08-01), Mori et al.
patent: 5347450 (1994-09-01), Nugent et al.
patent: 5353283 (1994-10-01), Tsuchiya
patent: 5394528 (1995-02-01), Kobayashi et al.
patent: 5440547 (1995-08-01), Easki et al.
patent: 5517497 (1996-05-01), LeBoudec et al.
patent: 5546549 (1996-08-01), Barrett et al.
patent: 5548639 (1996-08-01), Ogura et al.
patent: 5550589 (1996-08-01), Shiojiri et al.
patent: 5555542 (1996-09-01), Ogura et al.
patent: 5600606 (1997-02-01), Rao
patent: 5627986 (1997-05-01), Frankland
patent: 5649125 (1997-07-01), Tietjen et al.
"Deadlock-Free Routing Schemes on Multistage Interconnection Networks", IBM Technical Disclosure Bulletin, 35, 232-233, (Dec., 1992).
Adve, V.S., et al., "Performance Analysis of Mesh Interconnection Networks with Deterministic Routing", Transactions on Parallel and Distributed Systems, 225-246, (Mar. 1994).
Bolding, K., "Non Uniformities Introduced by Virtual Channel Deadlock Prevention", Technical Report 92-07-07, Department of Computer Science and Engineering, FR-35 University of Washington, Seattle, WA 98195, USA, Jul. 21, 1992).
Bolla, F.R., "A Neural Strategy for Optimal Multiplexing of Circuit and Packet-Switched Taffic", Department of Communications, Computer and Systems Science (DIST), University of Genova, 1324-1330.
Boura, Y.M., et al., "Efficient Fully Adaptive Wormhole Routing in n-dimensional Meshes", IEEE, 589-596, (1994).
Chien & J.H. Kim, A.A., "Planar-Adaptive Routing: Low-Cost Adaptive Networks for Multiprocessors", Pro. 19th International Symposium on Computer Architecture, 268-277, (May 1992).
Dally, W., "Performance Analysis of k-ary n-cube Interconnection Networks", IEEE Transactions on Computers, vol. 39, No. 6, 775-785, (Jun. 1990).
Dally, W., "Virtual-Channel Flow Control", IEEE, 60-68, (1990).
Dally, W., et al., "Deadlock-Free Message Routing in Multiprocessor Interconnection Networks", IEEE Transactions on Computers, C-36, 547-553, (May, 1987).
Dally, W.J., et al., "Deadlock-Free Adaptive Routing in Multicomputer Networks Using Virtual Channels", I.E.E.E. Transactions on Parallel and Distributed Systems, vol. 4, No. 4, 466-475, (Apr. 1993).
Duato, J., "A New Theory of Deadlock-Free Adaptive Routing in Wormhole Networks", I.E.E.E. Transactions on Parallel and Distributed Systems, vol. 4, No. 12, at 1320-1331, Dec. 1993.
Gallagher, R., "Scale Factors for Distributed Routing Algorithm", NTC '77 Conference Record, 2, at 2-1 through 2-5.
Glass, C.J., et al., "The Turn Model for Adaptive Routing", Pro. 19th International Symposium on Computer architecture, 278-287, (May 1992).
Gravano, L., et al. "Adaptive Deadlock- and Livelock-Free Routing with all Minimal Paths in Torus Networks", IEEE Transactions on Parallel and Distributed Systems, vol. 5, No. 12, 1233-1251, (Dec. 1994).
Jesshope, C.r., M.Y., "High Performance Communications in Processor Networks", High Performance Communications in Processor Networks, proc. 16th International Symposium on Computer Architecture at 150-157, May 1989.
Kirkpatrick, S., et al., "Optimization by Simulated Annealing", Science, May 13, 1993, vol. 220, No. 4598, 671-680.
Linder, D.H., et al., "An Adaptive and Fault Tolerant Wormhole Routing Strategy for k-ary n-cubes", I.E.E.E. Trans. on Computers, 2-12, (Jan. 1991).
Lui, Z., et al., "Grouping Virtual Channels for Deadlock-Free Adaptive Wormhole Routing", PARLE '93 Parallel Architectures and Languages Europe, 5th International PARLE Conference, Munich, Germany.backslash., 255-265, (Jun, 14-17, 1993).
Nuth, P., et al., "The J-Machine Network", IEEE, 420-423, (1992).
Shumay, M., "Deadlock-Free Packet Networks", Transputer Research and Applications 2, NATUG-2 Proceedings of the Second Conference of the North American Transputer Users Group, 140-177, (Oct. 18-19, 1989).
Synder, L., "Introduction to the Configurable, Highly Parallel Computer", 47-56, (Jan. 1982).
Talia, D., "Message-Routing Systems for Transputer-Based Multicomputers", IEEE Micro, vol. 13, No. 3, New York US,, 62-72, (Jun., 1993).
Wang, W., et al., "Trunk Congestion Control in Heterogeneous Circuit Switched Networks", IEEE, pp. 1156-1161.
Yang, C.S., et al., "Performance Evaluation of Multicast Wormhole Routing in 2D-Torus Multicomputers", IEEE, 173-178 (1992).
Yantchev, J., et al., "Adaptive, low latency, deadlock-free packet routing for networks of processors", IEEE Proceedings, 136, 178-186 (May 1989).
Fromm Eric C.
Kessler Richard E.
Oberlin Steven M.
Scott Steven L.
Cray Research Inc.
Lee Thomas C.
Wang Albert
LandOfFree
Method of handling arbitrary size message queues in which a mess does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of handling arbitrary size message queues in which a mess, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of handling arbitrary size message queues in which a mess will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-529559