Method of global planarization in fabricating integrated circuit

Details Method of global planarization in fabricating integrated circuit Method of global planarization in fabricating integrated circuit

1995-11-07

1999-03-23

Kight, John

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

438759, 438760, 438388, H01L 21465

Patent

active

058859004

ABSTRACT:
Global planarization of a non-planar substrate surface is accomplished using a sacrificial material in conjunction with an etching and chemical-mechanical polishing (CMP) technique. The sacrificial material has a greater rate of removal relative to the substrate during the CMP process and at a lesser rate relative to the material during the etching process. The use of the sacrificial material enables the etching process to substantially reduce the height of topographic features that occur in the non-planar surface. The CMP process is then performed on the etched material surface to produce a planarized material surface that is substantially free of feature dependent dishing. Such a process is useful for planarizing material layers in fabricating integrated circuit devices as well as for planarizing recessed structures in such devices.

REFERENCES:
patent: 4671851 (1987-06-01), Beyer et al.
patent: 4944836 (1990-07-01), Beyer et al.
patent: 5284804 (1994-02-01), Moslehi
patent: 5312512 (1994-05-01), Allman et al.
patent: 5362669 (1994-11-01), Boyd et al.
patent: 5491113 (1996-02-01), Murota
patent: 5516729 (1996-05-01), Dawson et al.
R.V. Joshi, "A New Damascene Structure for Submicrometer Interconnect Wiring", IEEE Electron Device Letters, vol. 14, No. 3, pp. 129-132, (Mar. 1993).
IBM Technical Disclosure Bulletin vol. 27, No. 4B (Sep. 1984).
IBM Technical Disclosure Bulletin, vol. 27, No. 8 (Jan. 1985).
IBM Technical Disclosure Bulletin, vol. 27, No. 6 (Nov. 1984).
IBM Technical Disclosure Bulletin, vol. 29, No. 2 (Jul. 1986).

Affiliated with

Also associated with

Rating

Method of global planarization in fabricating integrated circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of global planarization in fabricating integrated circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of global planarization in fabricating integrated circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2125037