Method of generating protected standard delay format file

Details Method of generating protected standard delay format file Method of generating protected standard delay format file

2006-10-31

2006-10-31

Lin, Sun James (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07131079

ABSTRACT:
A method of generating a protected standard delay format (SDF) file is disclosed. The interconnect delay descriptions of a SDF file are backwardly or forwardly integrated into the related cell delay descriptions according to their interconnection type to generate the protected SDF file. The total delay value of each signal path is the same as original, so that the simulation result generated by a simulator is not affected.

REFERENCES:
patent: 6587999 (2003-07-01), Chen et al.
patent: 6668359 (2003-12-01), Fakhry et al.
patent: 6766506 (2004-07-01), Ratzlaff et al.
“Automatic Method for Verifying NDR and Simulation Models”, Oct. 2001, IBM Technical Disclosure Bulletin, iss. 450, p. No. 1716 (8 pages).
Franzon et al., “Tutorial 1—Introduction to ASIC Design Methodology”, Spring 1999, rev. 99.1, pp. 1-32.
“IEEE Standard for Standard Delay Format (SDF) for the Electronic Design Process”, Dec. 2001, IEEE STD 1497-2001, 81 pages.

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