Method of generating multiple hardware description language...

Details Method of generating multiple hardware description language... Method of generating multiple hardware description language...

2006-06-20

2006-06-20

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07065734

ABSTRACT:
A method and computer program are disclosed for generating a hardware description language configuration from a generic phase locked loop architecture that include steps of: (a) receiving as input values for a set of configuration variables for a phase locked loop; (b) applying the values for the set of configuration variables to a generic top level model of the phase locked loop to generate a specific configuration of the phase locked loop from the generic top level model; and (c) generating as output a hardware description language code for the specific configuration of the phase locked loop.

REFERENCES:
patent: 5946478 (1999-08-01), Lawman
patent: 6542040 (2003-04-01), Lesea
patent: 6704908 (2004-03-01), Horan et al.
patent: 6747497 (2004-06-01), Ingino, Jr.
patent: 2004/0128641 (2004-07-01), Broberg et al.

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