Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-03-31
2001-02-13
Teska, Kevin J. (Department: 2768)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06189135
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an electron-beam data generating apparatus for converting layout pattern data into electron-beam data (EB data) for creating a mask to be used in a semiconductor fabrication process.
2. Description of the Prior Art
In order to manufacture a semiconductor integrated circuit (LSI), in general, after the design of the LSI has been completed, a circuit pattern of the LSI is created as a metallic thin film on a glass substrate. The metallic thin film forming the circuit pattern of the LSI is referred to as a mask. Semiconductor devices are then created by transferring the circuit pattern to locations on a silicon wafer sequentially one location after another by using the mask. A mask is created normally by, first of all, converting a circuit pattern resulting from a completed layout design into mask data having a data format readable by a mask drawing apparatus. In the following description, the circuit pattern, data input to the format-conversion process, is referred to as layout-pattern data which has a GDSII STREAM format. On the other hand, mask data output by the conversion is called as EB data.
When the designer creates layout-pattern data, a circuit pattern is entered for each fabrication process. At that time, it is necessary to enter figure data by providing a hierarchy thereto. The hierarchy comprises design layers. A segment is a drawing-region unit of the mask drawing apparatus. A mask is drawn by dividing the pattern of the mask into segment units.
FIG. 8
is a block diagram showing the configuration of a conventional electron-beam data generating apparatus for two design layers, two fabrication processes and two segments.
FIG. 9
is a diagram showing an example of an image figure of layout-pattern data. In this example, the number of fabrication processes match the number of design layers. It should be noted, however, that one fabrication process may correspond to a plurality of design layers.
In
FIG. 8
, reference numerals
1
and
2
denote layout-pattern data and a stream analyzing unit respectively. Reference numeral
3
is a reference sorting unit and reference numeral
4
denotes a hierarchy developing unit. Reference numerals
5
and
6
are a trapezoid division unit and a trapezoid-file sorting unit, respectively. Reference numeral
7
denotes a data compressing unit and reference numeral
8
is a format converting unit. Reference numerals
9
a
and
9
b
each denote EB data.
The hierarchy developing unit
4
comprises a hierarchy developing L
1
sub-unit
10
and a hierarchy developing L
2
sub-unit
11
for developing hierarchies for design layers L
1
and L
2
respectively. The trapezoid division unit
5
comprises a trapezoid division P
1
sub-unit
12
and a trapezoid division P
2
sub-unit
13
for carrying out trapezoid division processes on data developed for fabrication processes P
1
and P
2
, respectively. In addition, the trapezoid-file sorting unit
6
comprises a trapezoid-file sorting P
1
S
1
sub-unit
14
, a trapezoid-file sorting P
1
S
2
sub-unit
15
, a trapezoid-file sorting P
2
S
1
sub-unit
16
and a trapezoid-file sorting P
2
S
2
sub-unit
17
for carrying out trapezoid-file sorting processes for their respective combinations of the two fabrication processes P
1
and P
2
and segments S
1
and S
2
each used as a unit of mask-pattern creation. The data compressing unit
7
comprises a data compressing P
1
S
1
sub-unit
18
, a data compressing P
1
S
2
sub-unit
19
, a data compressing P
2
S
1
sub-unit
20
and a data compressing P
2
S
2
sub-unit
21
for sorting trapezoid files of their respective combinations of the two fabrication processes P
1
and P
2
and the two segments S
1
and S
2
. The format converting unit
8
comprises a format converting P
1
sub-unit
22
and a format converting P
2
sub-unit
23
for format conversion to generate the EB data
9
a
and the EB data
9
b
of the fabrication processes P
1
, and P
2
respectively.
First of all, from the layout-pattern data
1
created by the designer in the GDSII STREAM format, figure data of the stream data is read out by the stream analyzing unit
2
for each cell. At that time, only data of layers specified by parameter inputs is read in. Further, the stream format is checked and, in addition, data such as cell names and reference information is analyzed.
The reference sorting unit
3
then sorts reference files from the analyzed stream. Subsequently, the hierarchy developing unit
4
develops a cell hierarchical structure for each design layer, creating a flat figure on each of the fabrication processes. Then, the trapezoid division unit
5
carries out a trapezoid division process on the figure having a developed hierarchical structure for each fabrication process. The trapezoid-file sorting unit
6
then carries out a file sorting process on trapezoid data produced by the trapezoid division unit
5
for each segment. Subsequently, the data compressing unit
7
compresses the data for each fabrication process and each segment. Finally, the format converting unit
8
carries out format conversion for each fabrication process to produce a MEBES data format. The of processing steps described above result in the EB data
9
a
and the EB data
9
b.
In the hierarchy developing unit
4
, the design layer L
1
is processed by the hierarchy developing L
1
sub-unit
10
and, as the processing is completed, the design layer L
2
is processed by the hierarchy developing L
2
sub-unit
11
. In the trapezoid division unit
5
, figures developed by the hierarchy developing unit
4
undergo processing for the fabrication process P
1
by the trapezoid division P
1
sub-unit
12
and, as the processing is completed, undergo processing for the fabrication process P
2
by the trapezoid division P
2
sub-unit
13
. In the trapezoid-file sorting unit
6
, files of the figures completing the trapezoid division processing are sorted by using data such as the X-direction coordinate or a data code resulting from coding of a trapezoidal shape, a stripe or a segment as a key. First of all, processing for the fabrication process P
1
and the segment S
1
is carried out by the trapezoid-file sorting P
1
S
1
sub-unit
14
. When this processing is finished, processing for the fabrication process P
1
and the segment S
2
is carried out by the trapezoid-file sorting P
1
S
2
sub-unit
15
. When this processing is finished, processing for the fabrication process P
2
and the segment Si is carried out by the trapezoid-file sorting P
2
S
1
sub-unit
16
. When this processing is finished, processing for the fabrication process P
2
and the segment S
2
is carried out by the trapezoid-file sorting P
2
S
2
sub-unit
17
. In the data compressing unit
7
, processing for the fabrication process P
1
and the segment S
1
is carried out by the data compressing P
1
S
1
sub-unit
18
. When this processing is finished, processing for the fabrication process P
1
and the segment S
2
is carried out by the data compressing P
1
S
2
sub-unit
19
. When this processing is finished, processing for the fabrication process P
2
and the segment S
1
is carried out by the data compressing P
2
S
1
sub-unit
20
. When this processing is finished, processing for the fabrication process P
2
and the segment S
2
is carried out by the data compressing P
2
S
2
sub-unit
21
. In the format converting unit
8
, processing for the fabrication process P
1
is carried out by the format converting P
1
sub-unit
22
. When this processing is finished, processing for the fabrication process P
2
is carried out by the format converting P
2
sub-unit
23
.
Having a configuration described above, the conventional electron-beam data generating apparatus has a problem that it takes a long time to carry out the processing to convert layout-pattern data into EB data.
SUMMARY OF THE INVENTION
The present invention is implemented to solve the problem described above, and it is thus an object of the present invention to provide an electron-beam da
Garbowski Leigh Marie
Leydig , Voit & Mayer, Ltd.
Mitsubishi Electric Semiconductor Software Co. Ltd.
Teska Kevin J.
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