Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-02-01
2002-06-04
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06401230
ABSTRACT:
COPYRIGHT NOTICE
A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by any one of the patent disclosure, as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all copyright rights whatsoever.
BACKGROUND OF THE INVENTION
The present invention relates to computer-assisted methods and apparatus for generating electronic designs such as designs for digital integrated circuits. More specifically, the invention relates to improvements in the usefulness of “off-the-shelf” functional blocks for electronic designs.
Present Electronic Design Automation (EDA) systems for the design of electronic circuits, sometimes referred to as ECAD or electronic CAD systems, assist in the design of electronic circuits by providing a user with a set of software tools running on a digital computer. Such systems are provided with various architectures. In one widely used architecture, five major software program functions run on the ECAD system: a schematic editor, a compiler, a simulator, a verifier, and a layout program. Sometimes, the layout program forms part of the compiler. The schematic editor program allows the user of the system to enter and/or modify a schematic diagram of an electronic design using the display screen, generating a net list (summary of connections between components) in the process. An equivalent method for entering an electronic design involves providing a description of the design in a Hardware Description Language (HDL). Examples of HDLs include Verilog and VHDL. The syntax of a VHDL description is described in IEEE Standard VHDL Language Reference Manual (IEEE Std 1076-1987), which is incorporated herein by reference for all purposes and in its entirety. Like the schematic representation, the HDL representation also provides a net list.
The compiler takes the net list as an input, and using a component database puts all of the information necessary for layout, verification, and simulation into an object file or files. The verifier checks the input design (schematic or HDL) for design errors, such as multiple outputs connected together, overloaded signal paths, etc. and generates error indications if any such design problems exist. The simulator takes the object file(s) and simulation models, and generates a set of simulation results, acting on instructions, initial conditions, and input signal values provided to it either in the form of a file or user input.
Often a designer creates an electronic design from various functional blocks. For example, the designer may first create a functional block for a particular filter, then create a functional block for a buffer, and then one for a memory block, and so on. With the component functional blocks in hand, the designer makes the necessary connections between them to create the larger design, a project. It is often convenient to design reusable functional blocks for use in multiple electronic designs/projects. For example, a functional block that performs the computationally intensive steps of a fast Fourier transform or an inverse fast Fourier transform may find use in many integrated circuits (e.g., circuits for encoding and decoding audio and video information digitally and analyzing data from various scientific instruments). Various individuals and groups developing relevant electronic designs have created reusable functional blocks for fast Fourier transforms and inverse fast Fourier transforms.
A user simply inserts the functional block into his or her larger electronic design, makes the necessary connections to other features of the larger electronic design, and compiles the entire design per the normal procedure. The resulting compiled electronic design includes the off-the-shelf functional block integrated with other components of the design in a compiled form. This design can be then used to program a programmable logic device or layout an application specific integrated circuit (ASIC), for example. Such predefined off-the-shelf functional blocks are given various names in the EDA industry. Examples include megafunctions, cores, macrofunctions, and the like. For convenience, any such functional blocks will often be referred to herein as “megafunctions” or simply “functional blocks.”
The underlying design associated with a megafunction will be defined by various parameters. Examples include bus widths, buffer sizes, memory array dimensions, etc. Many megafunctions contain rigidly set values for the associated parameters. For example, a buffer functional block may require a buffer depth of 16 words and a buffer width of 32 bits. Unfortunately, this rigidity limits wide spread use of such megafunctions. While many users may need a particular type of buffer, only a small fraction of them can make use of functional blocks that specify a particular bus width or buffer size. Functional blocks having such rigidly set specifications arc frequently referred to as “non-parameterized” functional blocks or megafunctions.
To address the difficulty of non-parameterized megafunctions, “parameterized” megafunctions have been developed. Typically, these megafunctions take advantage of the ability of some Hardware Description Languages to encode parameters for which the user/developer can specify values. Collections or libraries of parameterized megafunctions are available. One example is the library of parameterized modules (“LPM”) developed under the guidance of the EDIF association. Examples of members of the library include adders, multipliers, comparators, etc. Generally, these functions are rather low level.
Unfortunately, there are various problems with these parameterized megafunctions. For many of the various Hardware Description Languages available, parameterization is a poorly developed feature. This may be because most Hardware Description Languages were designed for simulation, not design entry and synthesis. As a result, parameterization is not supported universally and fully in many Hardware Description Languages. The proprietary Hardware Description Language, AHDL, used to design programmable logic devices of Altera Corporation (San Jose, Calif.), does fully support parameterization. Thus, parameterized megafunctions written in AHDL may have a rich compliment of parameterization. Unfortunately, similar megafunctions written in other Hardware Description Languages such as VHDL or Verilog, typically cannot have the rich compliment of parameterization available in AHDL megafunctions. Unfortunately, non-proprietary Hardware Description Languages such as VHDL and Verilog are widely used in the industry.
What is needed therefore is an improved method of providing flexibility to a user in selecting parameters and other options associated with megafunctions. For example, it would be desirable to have a mechanism that allowed the rich parameterization available with AHDL to be available for use with other Hardware Description Languages, so that megafunctions written in such other languages could be fully parameterized.
SUMMARY OF THE INVENTION
The present invention provides software modules, referred to herein as “plug-ins,” which associate with megafunctions written in any Hardware Description Language to provide rich parameterization. To the user, the plug-ins present an interface (sometimes referred to as a “wizard”) allowing selection or setting of any number of important parameters for a particular megafunction. To the design compiler, parameterized megafunctions instantiated via a plug-in appear to be a non-parameterized functions of a type that may be easily handled (by, for example, VHDL and Verilog compilers). Plug-ins “plug into” a compiler or an application associated with the compiler, sometimes referred to as a “plug-in manager.” The plug-in manager creates compilable files from user-defined parameter settings passed by the plug-ins.
One aspect of the invention pertains to the operation of a plug-in or related application for setting options for a p
Ahanessians Razmik
LeBlanc Marcel A.
Altera Corporation
Beyer Weaver & Thomas LLP
Siek Vuthe
Wolf, Esq. Dean E.
LandOfFree
Method of generating customized megafunctions does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of generating customized megafunctions, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of generating customized megafunctions will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2914734