Method of generating cell library data for large scale...

Details Method of generating cell library data for large scale... Method of generating cell library data for large scale...

2008-01-15

2008-01-15

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07320116

ABSTRACT:
A method of generating library data for a cell constructed of interconnected MOS transistors, includes a resistance extraction step which extracts source and drain resistances according to source and drain region surface areas by using a resistance calculating formula or referring to a resistance extraction reference file which, when the source and drain regions have a first surface area region, treats the source and drain resistances as resistance values depending on the surface areas, and when the source and drain regions have a second surface area region larger than the first surface area region, treats the source and drain resistances as fixed resistance values; and a simulation step which generates an input-output characteristic for the cell from a netlist containing a MOS transistor model that includes the extracted source resistances and drain resistances and connection information for the model, and from input signals.

REFERENCES:
patent: 6219630 (2001-04-01), Yonezawa et al.
patent: 6421814 (2002-07-01), Ho
patent: 7139990 (2006-11-01), Singh et al.
patent: 2003/0088842 (2003-05-01), Cirit
patent: 2004/0163068 (2004-08-01), Fukita et al.
patent: 2000-133800 (2000-05-01), None
patent: 2003-256492 (2003-09-01), None

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