Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2007-10-09
2007-10-09
Hoang, Huan (Department: 2827)
Static information storage and retrieval
Addressing
Sync/clocking
C365S194000, C365S230080
Reexamination Certificate
active
11388720
ABSTRACT:
In a method of generating an internal clock for a semiconductor memory device, a doubled clock is generated during operation in a high-speed test mode in response to an external clock. A data clock is generated by delaying the doubled clock so that data read from a memory cell array in the semiconductor memory device is output in synchronization with the external clock. A doubled sync clock synchronized with the external clock is generated by delaying the data clock. An internal clock is generated during operation in the high-speed test mode by delaying the doubled sync clock by a delay amount that corresponds to a delay amount experienced in generation of an internal clock in response to the external clock during operation in a normal mode. Accordingly, the high-speed test operation of the semiconductor memory device can be efficiently performed.
REFERENCES:
patent: 5675274 (1997-10-01), Kobayashi et al.
patent: 6301190 (2001-10-01), Tsujino et al.
patent: 08-167890 (1996-06-01), None
patent: 10-2003-0071094 (2003-09-01), None
patent: 10-2004-0078473 (2004-09-01), None
Hoang Huan
Mills & Onello LLP
Samsung Electronics Co,. Ltd.
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