Method of generating an efficient stuck-at fault and...

Details Method of generating an efficient stuck-at fault and... Method of generating an efficient stuck-at fault and...

2006-06-06

2006-06-06

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C714S703000, C714S726000, C714S735000, C714S736000, C714S815000, C714S047300

Reexamination Certificate

active

07058909

ABSTRACT:
A method of generating a truncated scan test pattern for an integrated circuit design includes steps of: (a) receiving as input an integrated circuit design; (b) estimating a number of transition delay fault test patterns and a corresponding number of top-off stuck-at fault patterns to achieve maximum stuck-at fault and transition delay fault coverage; (c) truncating the estimated number of transition delay fault patterns to generate a truncated set of transition delay fault patterns so that the truncated set of transition delay fault patterns and the corresponding number of top-off stuck-at fault patterns achieve maximum stuck-at fault and transition delay fault coverage within a selected scan memory limit; and (d) generating as output the truncated set of transition delay fault patterns and the corresponding number of top-off stuck-at fault patterns.

REFERENCES:
patent: 2005/0066242 (2005-03-01), Wang et al.
Lin et al., “High-Frequency, At-Speed Scan Testing,” IEEE, Oct. 2003, pp. 17-25.
Wang et al., “DS0LFSR: A BIST TPG for Low Switching Activity,” IEEE, Jul. 2002, pp. 842-851.
Heragu et al., “FACTS: Fault Coverage Estimation by Test Vector Sampling,” IEEE, 1994, pp. 266-271.
Benware, B.R.; Effectiveness Comparisons of Outlier Screening Methods for Frequency Dependent Defects on Complex ASICs; LSI Logic Corporation and IC Design & Test Lab, Portland State University. Apr. 27-May 1, 2003, pp. 1-8.

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