Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-01-31
2006-01-31
Whitmore, Stacy A. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C714S039000
Reexamination Certificate
active
06993735
ABSTRACT:
A method of generating a test pattern for simulating and/or testing the layout of an integrated circuit includes the steps of generating a set of test patterns on a random basis, applying the set of test patterns to the integrated circuit using an automatic test equipment, determining the outputs of the integrated circuit, processing the outputs to determine whether predetermined test criteria are met, and, depending on a result of the processing step, generating a new set of test patterns based on the old set of test patterns by using a genetic algorithm. Accordingly, the method employs a genetic algorithm to optimize a set of random patterns based on measurements by using an automatic test equipment. Thereby, a set of worst case noise patterns can be selected automatically.
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Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Stemer Werner H.
Tat Binh
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