Method of generating a schematic driven layout for a...

Details Method of generating a schematic driven layout for a... Method of generating a schematic driven layout for a...

2006-07-25

2006-07-25

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07082589

ABSTRACT:
A method of generating a schematic driven layout for an integrated circuit design includes steps of: (a) receiving as input a representation of a integrated circuit design comprising a hierarchy of blocks; (b) selecting a block in the hierarchy of blocks that requires a physical design and that contains no missing components; (c) generating a physical design for the selected block so that the selected block is no longer a missing component of any other block; and (d) repeating steps (b) and (c) until a physical design has been generated for each block in the hierarchy of blocks.

REFERENCES:
patent: 5249133 (1993-09-01), Batra
patent: 5473546 (1995-12-01), Filseth
patent: 6009251 (1999-12-01), Ho et al.
patent: 6505323 (2003-01-01), Lipton et al.
patent: 2003/0018948 (2003-01-01), Chang et al.
U.S. Appl. No. 10/231,904, filed Aug. 30, 2002, Dillon et al.

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