Method of generating a physical netlist for a hierarchical...

Details Method of generating a physical netlist for a hierarchical... Method of generating a physical netlist for a hierarchical...

2006-02-21

2006-02-21

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07003753

ABSTRACT:
A method of generating a physical netlist for an integrated circuit design includes steps of: (a) receiving as input a representation of a core cell for a hierarchical integrated circuit design; (b) generating a physical netlist for a core cell model tile that maps logical ports of the core cell to physical ports of the core cell model tile; (c) including values for parasitic resistances connecting the logical ports of the core cell to the physical ports of the core cell model tile in the physical netlist for the core cell model tile; (d) connecting a hierarchical array of core cell model tiles so that the physical ports of each core cell model tile are connected to one another inside the array or mapped to an input/output port of the hierarchical array of core cell model tiles; and (e) generating as output a physical netlist of the hierarchical array of core cell model tiles.

REFERENCES:
patent: 5777529 (1998-07-01), Lowe

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