Method of gap filling

Details Method of gap filling Method of gap filling

1998-11-27

2001-03-20

Talbot, Brian K. (Department: 1762)

Coating processes

Direct application of electrical, magnetic, wave, or...

Plasma

C427S255370, C438S788000, C438S792000, C438S435000, C438S437000, C438S695000, C438S702000

Reexamination Certificate

active

06203863

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a method of a multi-step high density plasma (HDP) chemical vapour deposition (CVD), and more particularly to a method of filling a gap between conductive structures in a semiconductor device with dielectric material.
2. Description of the Related Art
In a semiconductor devices, multilevel conductive wiring and other conductors are normally isolated by inter-metal dielectric (IMD) layers. As the dimension of devices shrinks, the aspect ratio of the gap between conductive layers increases. The gap with a higher aspect ratio is more difficult to fill. On the other hand, as the distance between conductive layers and other conductors becomes shorter, the capacitance increases, so that the operating speed is limited. To achieve a higher efficiency with the shrinking dimension of devices, the dielectric layer between conductive layers are required to have characteristics such as being filled within the gap evenly and uniformly, preventing the water flow, and minimising the capacitance between conductive layers by using a low dielectric constant material.
Thus, it is important to deposit a high quality, interstice-free dielectric layer to fill a gap with a high aspect ratio. The dielectric layer is formed, for example, by CVD which is performed by introducing the precursor to the deposition surface, and after reaction, the material is deposited on the surface. Different kinds of CVD processes are in use, Such as atmospheric pressure CVD (APCVD), low pressure CVD (LPCVD), and plasma enhanced CVD (PECVD). To obtain high quality oxide by APCVD and LPCVD, a high deposition temperature such as about 650° C. to 850° C. is required. However, for some conductive material, for example, aluminium, such a high deposition temperature causes voids within oxide. Structures like voids absorb water, and thus, are not a proper IMD layer. By PECVD, plasma provides extra energy for reacting gases, and therefore, the deposition is performed in a lower temperature, for example, a temperature at about 400° C. or lower.
In a conventional method of forming a dielectric layer between conductive wiring, an interlayer is formed by PECVD using silane or tetra-ethyl-ortho-silicate (TEOS) as precursor. An accompanying spin-on-glass (SOG) layer is formed on the conductive wiring and to fill the gap therebetween. However, due to the characteristics of absorbing water and the formation of interstices, SOG layer cannot fill the gap completely. This phenomenon is even more obvious as the devices become smaller. Thus, a method to fill the gap with a high quality dielectric material is urgently in need to develop.
In addition, in a device with a smaller dimension, the conventional CVD cannot fill a gap with a higher aspect ratio completely. For example, using PECVD, interstices between conductive wiring are sealed by the deposited material. In the subsequent process, the interstices are open and contaminated. Therefore, the conductive wiring or the contact are damaged, and the device is degraded.
FIG.
1
and
FIG. 2
show a method of filling a gap by a conventional PECVD process. Referring to
FIG. 1
, an oxide layer
10
is formed on a substrate
12
by PECVD with TEOS as a precursor. On a upper part of the side wall of the conductive wiring
14
, an overhang
15
is formed. As the deposition continues, an interstice
16
is sealed as shown in FIG.
2
. The interstice
16
is formed as a seam along the conductive wiring lengthwisely. The seam is near the end of the conductive wiring, or is restricted in the bending part of the conductive wiring. In the subsequent process, the interstice
16
is very likely to be uncovered, so that chemical for polishing or the by-product for etching is trapped by the interstice. The trapped material within the interstice is very difficult to remove, and thus, the yield of the subsequent process is degraded.
The HDPCVD is intensively developed due to the characteristics as follows. The HDPCVD is performed in a lower deposition temperature compared to other CVD processes. In the commercial application, for example, by Novellus System, Inc, HDPCVD has been applied to form a high density, water proof, and planarized dielectric layer. In a HDPCVD system, a high density plasma is supplied from different sources, for example, electron cyclotron resonance, inductively coupled plasma, or transformer coupled plasma. During the deposition, the plasma produced by any mechanism is controlled by the bias sputtered portion. By controlling the bias relative to the substrate, the condition of deposition, the energy of the precursor gases, and the range to etch and sputter can be altered. By precisely controlling the steps of depositing IMD layers, it is possible to fill the gap more smoothly without forming interstice. Moreover, in other deposition process such as PECVD, overhang is formed on the upper side wall of the gap. The formation of overhang cause the formation of interstice or void within the dielectric layer. By HDPCVD, an etching process is provided during deposition to remove the overhang. Thus, the possibility of forming interstice or void is reduced.
Using HDPCVD in the invention for gap filling, an additional process of sputtering occurs simultaneously. The effect of gap filling of HDPCVD is better than the conventional CVD. During HDPCVD, ions are accelerated by biased portion to etch the material deposited on the surface of the substrate and sputter the etched material. Furthermore, a recess is formed in the substrate, for example, a recess formed by ion flux. When an oxide is deposited on the substrate by HDPCVD including bias sputtering the surface of the substrate is etched by the oxide. Normally, during bias sputtering most of the ions are inert argon ions. The chemical mechanism is hardly performed. On the contrary, the physical mechanism is in use. In the function of the etching speed of oxide during HDPCVD and the incident angle of etching ions, a higher etching speed is obtained with a larger incident angle. The incident angle dependence of bias sputtering in HDPCVD causes etching in the corner faster than etching the other part. Thus, the portion to seal interstices or voids are etching and sputtered into the gap, and a flat surface is obtain. This is a characteristic of HDPCVD. It is to be noted that for any process regarding plasma technique, a mechanism of etch sputtering and deposition is included. The sputtering speed of the HDPCVD discussed in the invention is a comparison with the sputtering characteristic of PECVD as a standard.
Another advantage of HDPCVD is that during the deposition of oxide layer, the deposition is not necessary to be performed in a high temperature. The process of fabricating devices are simplified, so that the time to expose the device under a high temperature environment is reduced. In the invention, three steps are performed under different deposition condition for gap filling without degrading the quality of the conductive wiring.
Deposition and etching are performed simultaneously during HDPCVD. By bias deposition, the material on the side wall of the conductive wiring is removed and recombined to fill the gap. As mentioned above, the deposition portion prevents the formation of overhang on top corner of the conductive wiring, and thus, a better gap filling effect is obtained. It is to be noted that during HDPCVD, the conductive wiring or the passivation layer is damaged for over etching. Therefore, some deposition or other process is adjusted to protect the conductive wiring or the IMD layer. The above three steps of HDPCVD are used to fill the gap within the conductive wiring. The etching and deposition rate for each step are different.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a method of gap filling by using HDPCVD. The process includes different steps to control the speed of gap filling and protect structures of devices during deposition or etching.
To achieve these objects and advantages, and in accordance with the purpo

Affiliated with

Also associated with

Rating

Method of gap filling does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of gap filling, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of gap filling will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2509683