Method of full semiconductor chip timing closure

Details Method of full semiconductor chip timing closure Method of full semiconductor chip timing closure

2005-10-24

2010-06-01

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07730437

ABSTRACT:
A method of full semiconductor chip timing closure includes the steps of determining a system level place and route. Next, a static timing analysis for each of a number of subsystems is performed. Finally, a full chip static timing analysis is performed.

REFERENCES:
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patent: 6519749 (2003-02-01), Chao et al.
patent: 6567957 (2003-05-01), Chang et al.
patent: 6567967 (2003-05-01), Greidinger et al.
patent: 6845494 (2005-01-01), Burks et al.
patent: 6877139 (2005-04-01), Daga
patent: 7093208 (2006-08-01), Williams et al.

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