Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-06-11
2004-08-10
Gurley, Lynne (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S636000, C438S637000, C438S638000, C438S782000
Reexamination Certificate
active
06774028
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to a method of forming a wiring structure by using a via-first dual damascene method which is used for forming a multi-layer wiring structure and the like of a semiconductor device. More particularly, the present invention relates to a method of forming a wiring structure by using a via-first dual damascene method in which a development rate of a photo resist film is optimized.
BACKGROUND OF THE INVENTION
As a method of forming wiring conductors having a multi-layer structure in a semiconductor integrated circuit device, there is known a damascene wiring technology. Among the damascene wiring technology, a dual damascene technology has merits of simplifying a manufacturing process and shortening a Turn-and-Around-Time (TAT), and of greatly reducing manufacturing costs of a semiconductor integrated circuit device. In the dual damascene technology, wiring trenches for forming upper layer wiring conductors and via holes or contact holes (hereafter, referred to as via holes including both of the via holes and contact holes) for forming vias or via conductors which couple the upper layer wiring conductors and lower layer wiring conductors or substrates are formed in an insulating film, and thereafter the wiring trenches and the via holes are filled at the same time with a metal material to form the upper layer wiring conductors and the via conductors at the same time. Especially, among the dual damascene method, a via-first dual damascene method in which via holes are formed before forming wiring trenches has the merit of reducing unevenness of a photo resist film in an etching process for forming the via holes. Thereby, it becomes possible to perform minuter work of the dual damascene structure. As the photo resist, there are known a positive type photo resist and a negative type photo resist. In the dual damascene method, the positive type photo resist is generally used, because the positive type photo resist has high image resolution and many kinds of positive type photo resist materials are available.
With reference to the drawings, an explanation will be made on an example of a method of forming wiring conductors according to a conventional via-first dual damascene method.
FIGS. 11A-11C
,
FIGS. 12A-12C
and
FIGS. 13A-13C
are cross sectional views each illustrating a structure of a workpiece during a process of fabricating a dual damascene structure according to the conventional via-first dual damascene method.
First, as shown in
FIG. 11A
, an etching stopper film
7
made of SiCN is formed on a lower wiring layer
8
. Then, an interlayer insulating film
6
made of SiO
2
is formed on the etching stopper film
7
, and an etching stopper film
5
made of SiC is formed on the interlayer insulating film
6
. Further, an interlayer insulating film
4
made of ladder oxide is formed on the etching stopper film
5
, and SiO
2
is plasma deposited on the interlayer insulating film
4
, thereby a cap film
3
is formed.
Then, a bottom anti-reflective coating (BARC) not shown in the drawing is applied on the cap film
3
, and further a photo resist film not shown in the drawing is applied thereon. The photo resist film is then exposed by using KrF (krypton fluoride) excimer laser, and thereafter developed. Thereby, a via hole pattern is formed by a photolithography technology.
As shown in
FIG. 11B
, by using the photo resist film (not shown in the drawing) in which the via hole pattern is formed as a photo mask, the bottom anti-reflective coating (not shown in the drawing), the cap film
3
, the interlayer insulating film
4
, the etching stopper film
5
and the interlayer insulating film
6
are etched, thereby a via hole
9
reaching the etching stopper film
7
is formed. In the drawing, only one via hole
9
is shown. However, it is also possible to form many via holes at the same time. Thereafter, by using O
2
plasma ashing and organic remover, the photo resist film and the bottom anti-reflective coating are removed.
Next, as shown in
FIG. 11C
, another bottom anti-reflective coating
2
made of organic material is formed on the cap film
3
and within the via hole
9
. In this case, the bottom anti-reflective coating
2
is formed such that the via hole
9
is completely filled with the material of the bottom anti-reflective coating
2
. That is, the via hole
9
is full-filled with the material of the bottom anti-reflective coating
2
.
As shown in
FIG. 12A
, positive type photo resist material is applied on the bottom anti-reflective coating
2
and, thereby, a photo resist film
11
is formed on the bottom anti-reflective coating
2
.
Then, as shown in
FIG. 12B
, the photo resist film
11
is exposed by using KrF excimer laser, and thereafter developed. Thereby, a trench pattern is formed by a photolithography technology.
As shown in
FIG. 12C
, by using the photo resist film
11
as a mask, the bottom anti-reflective coating
2
is anisotropically etched back by O
2
plasma. In this case, a portion of the bottom anti-reflective coating
2
within the via hole
9
is etched away at least up to the level corresponding to the etching stopper film
5
.
As shown in
FIG. 13A
, by using the photo resist
11
as a mask, the cap film
3
and the interlayer insulating film
4
are etched away and a wiring trench or groove
10
is formed.
Then, as shown in
FIG. 13B
, by using O
2
plasma ashing and organic remover, the photo resist film
11
and the bottom anti-reflective coating
2
are removed.
As shown in
FIG. 13C
, the via hole
9
and the wiring trench
10
are filled with conductive material
12
such as Cu, and, by using a Chemical Mechanical Polishing (CMP) method, the surface of the cap film
3
is planarized. Thereby, all the conductive material
12
on the cap film
3
and almost all portion of the cap film
3
are removed, and a desired wiring structure is completed.
However, in the conventional method of forming wiring conductors mentioned above, it is necessary, in the process illustrated in
FIG. 12C
, to anisotropically etch back the bottom anti-reflective coating
2
made of organic material to a thickness of 300-600 nm. In such anisotropic etching back, it is difficult to precisely control the lateral size of the via hole and the like.
In order to solve such problem, there is known a method in which a via hole is not filled wholly with a material of a bottom anti-reflective coating but the via hole is partially filled with the material. That is, the via hole is not full-filled but partial-filled with the material of the bottom anti-reflective coating. With reference to the drawings, an explanation will be made on such method.
FIGS. 14A-14C
,
FIGS. 15A-15C
and
FIGS. 16A-16C
are cross sectional views each illustrating a structure of a workpiece during a process of fabricating a dual damascene structure according to such partially filling via-first dual damascene method. In these drawings, portions identical or corresponding to those in
FIGS. 11A-11C
,
FIGS. 12A-12C
and
FIGS. 13A-13C
used before for illustrating the above-mentioned fully filling method are designated by the same reference numerals, and detailed description thereof is omitted here.
First, as shown in
FIG. 14A
, on a lower wiring layer
8
, an etching stopper film
7
, an interlayer insulating film
6
, an etching stopper film
5
, an interlayer insulating film
4
, and a cap film
3
are formed in this order. Then, a bottom anti-reflective coating (BARC) not shown in the drawing is applied on the cap film
3
, and further a photo resist film not shown in the drawing is formed thereon. The photo resist film is then exposed by using KrF (krypton fluoride) excimer laser, and thereafter developed. Thereby, a via hole pattern is formed by a photolithography technology.
As shown in
FIG. 14B
, by using the photo resist film (not shown in the drawing) in which the via hole pattern is formed as a photo mask, the bottom anti-reflective coating (not shown in the drawing), the cap film
3
, the interlayer insulating film
4
, the
Gurley Lynne
NEC Electronics Corporation
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