Method of forming wiring in semiconductor device

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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Reexamination Certificate

active

06228764

ABSTRACT:

This application claims the benefit of Korean Applications No. 97-59501 filed Nov. 12, 1997, and No. 98-36141 filed Sep. 2, 1998, which are hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a method of forming a wiring in a semiconductor device. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for preventing an electromigration in the wiring of the semiconductor device.
2. Discussion of the Related Art
Aluminum (Al) has a desirable electrical conductivity and a good adherence to an insulating film and is easy to be formed in fabricating a semiconductor. Thus, aluminum (Al) and its alloy are one of the most preferred materials in fabricating a semiconductor device. In a physical vapor deposition (PVD) for depositing aluminum and its alloy, a concentration of copper (Cu) in a thin film to be formed is easily adjusted by altering the concentration of Cu in a target material.
A vertical wiring of contact/via layers having a high aspect ratio must be formed in fabricating a VLSI device. However, the contact/via layer is not completely filled by the PVD due to a poor step coverage. Accordingly, chemical vapor deposition (CVD) providing a good step coverage has been chosen to improve a problem of the PVD. During a CVD process, a surface chemical reaction is occurred to decompose a source gas and an intended material is deposited at the surface of a substrate.
Nevertheless, even the CVD has a drawback in depositing two different materials simultaneously although depositing a single material is relatively easy. Therefore, an addition of Cu in a later process is essential in depositing Al to reduce an electromigration. In the electromigration, aluminum atoms are diffused into the substrate at high current concentration regions. Especially, voids are formed at regions in contact with silicon or stepped regions, when a current passes through an aluminum wiring. Thus, as the wire becomes thinner, it is disconnected at the end. Accordingly, in the background art, a simultaneous deposition of aluminum and copper has been studied to employ the CVD process in forming a wiring in the semiconductor device.
However, the simultaneous deposition of aluminum and copper using CVD to form a wiring in a semiconductor device has the following problems.
It is very difficult to select different source gases for aluminum and copper which do not react with each other and have similar deposition temperatures. In addition, the amount of copper to be added into the source gases is difficult to be determined.
Further, when a pure copper is used to add the copper through a diffusion to chemically deposited aluminum, an intermetallic composition between aluminum and copper is formed, so that it increases an overall resistivity of the thin film and interferes an effective diffusion of the copper. As a result, an extra amount of the pure copper is needed to complete the diffusion process according to the background art.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a method of forming a wiring in a semiconductor device that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a method of forming a wiring in a semiconductor device which reduces a an electromigration in the wiring.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a method of forming a wiring in a semiconductor device includes the steps of forming a barrier layer on a semiconductor substrate, depositing a pure first metal film on the barrier layer, forming an alloy film of first, and second metals on the pure first metal film, and diffusing the second metal in the alloy film of first, and second metals into the first metal film.
In another aspect of the present invention, a method of forming a wiring in a semiconductor device having a semiconductor substrate includes the steps of forming a barrier layer on the semiconductor substrate, forming a first metal layer on the barrier layer, forming a first alloy layer containing the first metal layer and a second metal layer on the first metal layer, and forming a second alloy layer by diffusing between the first metal layer and the first alloy layer.
In another aspect of the present invention, a method of forming a wiring in a semiconductor device having a semiconductor substrate, comprising the steps of forming a barrier layer on the semiconductor substrate, forming a first metal layer on the barrier layer, forming a first alloy layer containing the first metal layer and a second metal layer on the first metal layer, forming a second metal layer, and forming a second alloy layer by diffusing between the first metal layer and the first alloy layer.
In a further aspect of the present invention, a method of forming a wiring in a semiconductor device having a semiconductor substrate, comprising the steps of forming a barrier layer on the semiconductor substrate, forming a first alloy layer containing first and second metal layers on the barrier layer, forming the first metal layer on the first alloy layer, and forming a second alloy layer by diffusing between the first metal layer and the first alloy layer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 4897709 (1990-01-01), Yokoyama et al.
patent: 5572072 (1996-11-01), Lee

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