Method of forming viaducts in semiconductor material

Details Method of forming viaducts in semiconductor material Method of forming viaducts in semiconductor material

1976-09-29

1977-11-22

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

96 36, 156657, 156661, 156663, 427 82, B23P 1500, B23P 2506, B44C 122

Patent

active

040594807

ABSTRACT:
This method of forming viaducts or "through-holes" in semiconductor material for transistor and integrated circuit fabrication and especially for ink jet printing systems forms viaducts of uniform diameter without critical registration of masks.
A seed layer of Cr-Au is sputtered onto a silicon-dioxide substrate. The viaducts or holes to be made are imaged by a photoresist process with a 5 .mu. thick photoresist on this seed layer. A 4 .mu. thick gold layer is now applied on the seed layer by a plating process. After the dissolution of the photoresist this layer contains the hole pattern with the holes having the required diameter. In order to make a through-hole, the substrate has to be etched. For that purpose, the bare substrate surface is covered with photoresist and exposed from the back through gold holes, and subsequently developed. Problems owing to light diffraction at the edges of the gold with respect to the great distance of the gold mask - photoresist layer are not anticipated here because of the large holes and the high tolerances in this process step. Prior to etching the substrate, the gold layer with the hole pattern is covered by photoresist so that the substrate etching can take place from one side only. Now the substrate is etched until all of the gold holes are free. In that process, the extent of the substrate sub-etching is of small importance as the viaduct or hole diameter is defined by the gold mask. The photoresist is removed and the exposed substrate surfaces are protected against chemical reactions with the ink by a vapor-deposition of a protective layer.

REFERENCES:
patent: 3202094 (1965-08-01), Smallman
patent: 3313626 (1967-04-01), Whitney
patent: 3576669 (1971-04-01), Filip
patent: 3742229 (1973-06-01), Smith et al.
patent: 3958255 (1976-05-01), Chiou et al.
IBM Technical Disclosure Bulletin, vol. 15, No. 11, Apr. 1973, Electron-Beam Mask Useful in Microfabrication Processes by E. A. Giess, L. Kuhn and B. A. Scott, pp. 3309 and 3310.

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