Method of forming via

Details Method of forming via Method of forming via

1999-12-17

2001-06-12

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S620000, C438S627000, C438S637000, C438S639000, C438S629000, C257S649000, C257S698000, C257S750000

Reexamination Certificate

active

06245667

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial No. 88117958, filed Oct. 18, 1999.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of forming a via that leads to a semiconductor device. More particularly, the present invention relates to a method of forming a landed via according to the borderless design rule.
2. Description of the Related Art
Before the development of techniques for forming deep sub-micron semiconductor devices, critical dimension (CD) of devices used to be quite large. Even if there is some misalignment in carrying out photolithographic process so that the vias are slightly offset, subsequently formed contacts can still land on the desired metallic lines. Operating characteristics of the device are affected very little by the misalignment.
However, when techniques for fabricating deep sub-micron devices are employed, critical dimensions of devices shrink considerably. Very small misalignment of vias or plugs often can have considerable effect on the operating characteristics of the devices. Alignment of vias and plugs becomes critical especially when the desired dimensions of a device exceed or approach the acceptable tolerance of the fabricating equipment. Hence, the conventional method is incapable of fabricating vias or plugs that land exactly on the desired locations according to deep-submicron device specification.
Therefore, innovative techniques for forming borderless vias or plugs are required in order to fabricate deep submicron devices. In particular, the formation of interconnects between a large number of layers to form a multi-level interconnect (MLM) system depends very much on the capacity to form high-quality borderless vias or plugs.
FIG. 1
is a schematic cross-sectional view of an ideal borderless via structure, and
FIG. 2
is a schematic cross-sectional view of an actual borderless via structure illustrating the effect of microloading after a metallic layer is patterned to form a metallic line.
As shown in
FIG. 1
, the edges of an ideal metal line
102
and its associated barrier layer
104
are almost vertical after patterning. Hence, a subsequently formed via
106
is able to land on the barrier layer
104
. When a plug
108
is formed inside the via
106
, the plug
108
makes contact with the barrier layer
104
without touching the metallic line
102
.
As shown in
FIG. 2
, due to microloading in the etching operation, a rectangular metallic line
102
and barrier layer
104
profile like the one in
FIG. 1
is difficult to obtain. Instead, the patterned metallic line
202
and the barrier layer
204
have a trapezoidal profile. The tapering shape of the trapezoidal structure reduces the surface area at the top of the barrier layer
204
. When a borderless via
206
is formed over the barrier layer
204
, a portion of the via
206
falls outside the top surface of the barrier layer
204
and the sidewall of the metallic line
202
is exposed. Subsequently, if a plug
208
is formed inside the via
206
, the plug
208
not only makes contact with the barrier layer
204
, but also makes contact with the metallic line
202
.
In general, a titanium silicide (TiN) layer is first deposited over the interior surface of the via
206
before the formation of the plug. The titanium silicide layer is able to strengthen the adhesion of the plug
208
. However, if the titanium silicide layer is formed by a nitridation procedure, gaseous nitrogen (N
2
) may react with the metallic material on the metallic line
202
(usually an aluminum-copper alloy) to form aluminum nitride (AlN). Consequently, resistivity of the plug
208
increases leading to electron migration and reliability problems for the devices.
SUMMARY OF THE INVENTION
The invention provides a method of forming a landed via. The method includes providing a substrate, and then forming a stacked structure comprising a conductive line made from an aluminum-copper alloy and a first barrier layer. The stacked structure has a trapezoidal profile with sloped sides. A second barrier layer is formed over the stacked structure and the substrate. The second barrier layer is etched back to form spacers on the sloped sidewalls of the stacked structure. A dielectric layer is formed over the stacked structure, the spacers and the substrate. A via is formed in the dielectric layer. The via exposes a portion of the first barrier layer and the spacer.
In this invention, spacers capable of serving as a barrier are formed over the tapering sidewalls of the metallic line and the barrier layer before vias and plugs are formed.
Since the tapering sidewalls of the metallic line and the barrier layer are covered by spacers, the vias are isolated from the underlying metallic line and barrier layer. Even if the via is formed according to the borderless design specification and does not land directly on the barrier layer, the via still does not lead directly to the surface of the metal line. Therefore, a subsequently formed plug inside the via has no direct contact with the metal line and cannot result in a higher resistivity and electron migration.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 6054380 (2000-04-01), Naik

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