Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Patent
1998-03-09
2000-03-07
Bowers, Charles
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
438787, 438788, 148116, 148163, H01L 2176
Patent
active
060339985
ABSTRACT:
Provided is a method of fabricating gate dielectric layers having variable thicknesses and compositions over different regions of a semiconductor wafer. In a preferred embodiment of the present invention, a gate oxide layer is first grown over the various regions. Regions that are to have a relatively thicker, unhardened gate dielectric are masked and the wafer is exposed to a remote low energy nitrogen plasma. After the nitridization process is completed, the mask is removed and the wafer is exposed to further oxidation. The regions where oxynitrides have been formed act as a barrier to the oxidation process. Consequently, different oxide thicknesses can be grown on the same wafer, thinner and hardened where nitridization has been performed, and thicker and not hardened in those regions that were masked during the nitridization. Variable thickness gate dielectrics in accordance with the present invention may be particularly advantageous in semiconductor integrated circuits involving both digital and analog devices.
REFERENCES:
patent: 4151537 (1979-04-01), Goldman et al.
patent: 4257832 (1981-03-01), Schwabe et al.
patent: 4306353 (1981-12-01), Jacobs et al.
patent: 4438157 (1984-03-01), Romano-Moran
patent: 4621277 (1986-11-01), Ito et al.
patent: 4849366 (1989-07-01), Hsu et al.
patent: 4869781 (1989-09-01), Euen et al.
patent: 5258333 (1993-11-01), Shappir et al.
patent: 5356722 (1994-10-01), Nguyen et al.
patent: 5397748 (1995-03-01), Watanabe et al.
patent: 5429965 (1995-07-01), Shimoji
patent: 5434109 (1995-07-01), Geissler et al.
patent: 5464783 (1995-11-01), Kim et al.
patent: 5478765 (1995-12-01), Kwong et al.
patent: 5571734 (1996-11-01), Tseng et al.
patent: 5573974 (1996-11-01), Hwang
patent: 5620910 (1997-04-01), Teramoto
M. Bhat, et al., "Effects of Chemical Composition on the Electrical Properties of NO-Nitrided SiO.sub.2," Appl. Phys. Lett., vol. 66, pp. 1225-1227 (1995).
C.T. Liu, et al, "High Performance 0.2 .mu.m CMOS with 25 A Gate Oxide Grown on Nitrogen Implanted Si Substrates," IEDM, pp. 499-502 (1995).
D.T. Grider, et al., "A 0.18 .mu.m CMOS Process using Nitrogen Profile-Engineered Gate Dielectrics," Symp. on VLSI Technology Digest of Tech. Papers, pp. 47-48 (1997). [Not yet received at libraries.].
S.V. Hattangady, et al., "Ultrathin Nitrogen-Profile Engineered Gate Dielectric Films," IEDM, pp. 495-498 (1996).
S.V. Hattangady, et al., "Controlled Nitrogen Incorporation at the Gate Oxide Surface," Appl. Phys. Lett., vol. 66, pp. 3495-3497 (1995).
Aronowitz Sheldon
Chan David
Haywood John
Kimball James
Lee David
Bowers Charles
Kilday Lisa
LSI Logic Corporation
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