Method of forming unlanded via hole

Details Method of forming unlanded via hole Method of forming unlanded via hole

1999-06-09

2000-07-04

Picardat, Kevin M.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438584, 438618, 438622, 438625, H01L 214763

Patent

active

060838256

ABSTRACT:
An improved method of fabricating an unlanded via hole on a semiconductor substrate is provided. A conductive line and a patterned anti-reflection coating layer are sequentially formed on the substrate wherein the patterned anti-reflection coating layer has a smaller width than the conductive line and a portion of the conductive layer is exposed by the patterned anti-reflection coating layer. A planarized dielectric layer is formed over the substrate to cover the patterned anti-reflection coating layer and the conductive line. A via hole is formed in the planarized dielectric layer to expose portions of surface and sidewalls of the patterned anti-reflection coating layer as well as the conductive line.

REFERENCES:
patent: 5880030 (1999-03-01), Fang et al.
patent: 5935868 (1999-08-01), Fang et al.

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