Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2000-06-21
2001-06-12
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S594000, C438S596000, C438S197000, C438S585000, C438S216000, C438S287000, C438S261000, C438S275000, C438S591000
Reexamination Certificate
active
06245652
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is generally related to semiconductor processing, and, more particularly, to the manufacture transistors having ultra thin oxide layers.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices. etc. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. Generally, at least in the field of microprocessors, the larger the drive current through a transistor, the faster the transistor, and devices comprised of such transistors, will operate.
As is well known to those skilled in the art, the drive current is a function of, among other things, the voltage applied across the transistor. The operating voltage of modern semiconductor devices has continued to decrease over the years. One reason for the decrease in the operating voltage is that it reduces the amount of power consumed by the device when it is operating Reducing power consumption may be useful in many applications. e.g. portable computers, due to the limited life of the batteries used in such devices for power. However, while decreasing the operating voltage of modern semiconductor devices has reduced the power consumed by such devices, it has also, all other things being equal, resulted in a decrease in the drive current through the transistor. As stated above, reductions in the drive current through a transistor tend to reduce the ability of semiconductor devices. e.g., microprocessors, to operate at increasingly faster speeds. All other things being equal, one way to increase the drive current, and thus operating speed of semiconductor devices, is to reduce the thickness of the gate dielectric, typically a layer of silicon dioxide. Thus, there is a drive within the semiconductor industry to reduce the thickness of the gate dielectric layers used in semiconductor devices to increase the speed of operation of the device.
There are also other problems associated with modern gate dielectric layers used in integrated circuit devices. For example, in PMOS transistors, the gate conductor is typically doped with a P
+
dopant material such as boron. However, the boron dopant tends to penetrate the gate dielectric layer and the surface of the silicon substrate. One problem such penetration causes is it tends to lower the threshold voltage of the semiconductor device, thus making breakdown a greater possibility. Moreover, the boron penetration of the gate dielectric layer tends to degrade the quality of the gate dielectric. In effect, if there is enough boron penetration, the life of the transistor may be dramatically shortened. Additionally, for NMOS technology, hot carrier currents can be problematic. By way of background, hot carrier currents are electrons traveling between the source and drain of a transistor that pass through the gate oxide to the gate conductor. In effect, these hot carrier currents tunnel through the gate dielectric layer. This problem can also reduce the life expectancy of a semiconductor device.
The present invention is directed to a method and semiconductor device for solving some or all of the aforementioned problems.
SUMMARY OF THE INVENTION
The present invention is directed to a semiconductor device having an ultra thin, reliable gate dielectric and a method for making same. The method comprises forming a first process layer comprised of a gate dielectric material above the surface of a semiconducting substrate, and reducing the thickness of the first process layer. The method continues with the formation of a second process layer comprised of a material having a dielectric constant greater than seven above the first process layer, and forming a third process layer comprised of a gate conductor material above the second process layer. The method further comprises patterning the first, second and third process layers to define a gate conductor and a composite gate dielectric comprised of a portion of said first and second process layers, and forming at least one source/drain region in the substrate.
The present invention is also directed to a transistor comprised of a composite gate dielectric positioned above a semiconducting substrate, and a gate conductor positioned above the composite gate dielectric. The composite gate dielectric is comprised of a first process layer comprised of a nitrogen doped oxide positioned above the surface of the substrate, and a second process layer comprised of a material having a dielectric constant greater than seven positioned above the first process layer. The device further comprises at least one source/drain region formed in the substrate.
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Fulford H. Jim
Gardner Mark I.
Kwong Dim-Lee
Advanced Micro Devices , Inc.
Luu Chuong A
Smith Matthew
Williams Morgan & Amerson P.C.
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