Method of forming ultra-short channel and elevated S/D MOSFETS w

Details Method of forming ultra-short channel and elevated S/D MOSFETS w Method of forming ultra-short channel and elevated S/D MOSFETS w

1999-02-12

2000-09-12

Smith, Matthew

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

438307, 438589, 438622, H01L 2100

Patent

active

061177121

ABSTRACT:
The method includes forming a buried oxide layer in a substrate. A pad oxide layer is then formed on the substrate. A silicon nitride layer is pattered on the surface of the pad oxide. Then, a thick field oxide (FOX) is formed on the pad oxide layer. Sidewall spacers are formed on the side walls of the opening of the silicon nitride layer. Next, the FOX is etched. An ion implantation is performed for adjusting the threshold voltage and anti-punch-through implantation. Subsequently, a dielectric with high permittivity is deposited along the surface of the substrate. The dielectric layer may be formed by a nitride technique. A conductive layer composed of metal or alloy is then formed on the dielectric layer and refilled into the opening. A chemical mechanical polishing is used to remove the dielectric layer, silicon nitride and the spacers such that the conductive layer remains only in the opening. The residual nitride and spacers are removed by hot phosphor acid solution. Source and drain are next created. The pad oxide layer and the FOX are then removed. Then, the lightly doped drain (LDD) are formed. A self-aligned silicide (SALICIDE) layer is formed on the substrate exposed by the gate.

REFERENCES:
patent: 5434093 (1995-07-01), Chau et al.
patent: 5583064 (1996-12-01), Lee et al.
patent: 5705405 (1998-01-01), Cunningham
patent: 5773348 (1998-06-01), Wu
patent: 5877056 (1999-03-01), Wu
patent: 5956580 (1999-09-01), Wu
patent: 6008079 (1999-12-01), Wu

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