Method of forming top metal contact to antifuse

Details Method of forming top metal contact to antifuse Method of forming top metal contact to antifuse

1999-12-27

2002-03-26

Hiteshew, Felisa (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

C438S696000

Reexamination Certificate

active

06362102

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of forming a self-aligned antifuse in the fabrication of integrated circuits.
(2) Description of the Prior Art
FIG. 1
is a flowchart of a typical antifuse cell process flow. In the fabrication of antifuse cells for programmable gate arrays, an antifuse material layer is deposited, patterned and etched (step
11
), followed by a blanket intermetal dielectric deposition (step
12
). Subsequently, a mask is used to open a contact to the antifuse (step
13
), followed by the antifuse contact etch (step
15
) and top metal deposition (step
16
).
FIG. 2
illustrates a typical antifuse cell of the prior art. A metal plug
20
is shown within a substrate
10
. Antifuse material
30
has been deposited and patterned overlying the metal plug. Intermetal dielectric layer
40
has been deposited. A contact opening has been opened in the intermetal dielectric layer
40
. A barrier layer
48
, such as titanium nitride, is deposited over the intermetal dielectric layer
40
and within the opening followed by top metal layer
50
.
However, this method has encountered programming yield failures due to the following reasons: 1) generation of excessive polymer at the antifuse contact area during etching, 2) antifuse contact area is limited by the antifuse contact via size, 3) antifuse alignment process margin, 4) ineffectiveness of the cleaning process in cleaning the generated polymer off the top of the antifuse, and 5) some areas inside circuits are unusable because of programming yield. It is desired to form an antifuse cell without opening a contact to the antifuse material.
U.S. Pat. Nos. 5,920,109 to Hawley et al and 5,763,299 to McCollum et al teach the formation of oxide spacers on the sidewalls of an antifuse. U.S. Pat. No. 5,602,053 to Zheng et al teaches formation of an antifuse structure.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of fabricating an antifuse cell for programmable gate array.
A further object of the invention is to provide a self-aligned method of fabricating an antifuse cell.
Yet another object is to provide a method of fabricating an antifuse cell where the fuse contact area is not limited by fuse via size.
A still further object is to provide a method of fabricating an antifuse cell having an increased contact area between the top metal and the antifuse.
In accordance with the objects of this invention a method for fabricating a self-aligned antifuse cell is achieved. An antifuse is provided overlying a metal plug in an insulating layer on a semiconductor substrate. A dielectric layer is deposited overlying the antifuse. The dielectric layer is etched to form dielectric spacers on the sidewalls of the antifuse. A top metal layer is deposited overlying the antifuse and dielectric spacers and patterned to complete the antifuse cell in an integrated circuit device.


REFERENCES:
patent: 5272101 (1993-12-01), Forouhi et al.
patent: 5387812 (1995-02-01), Forouhi et al.
patent: 5602053 (1997-02-01), Zheng et al.
patent: 5670818 (1997-09-01), Forouhi et al.
patent: 5763299 (1998-06-01), McCollum et al.
patent: 5920109 (1999-07-01), Hawley et al.

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