Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Having heterojunction
Reexamination Certificate
2001-11-26
2004-06-22
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Having heterojunction
C438S348000, C438S359000, C438S692000
Reexamination Certificate
active
06753234
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to bipolar transistors and, more particularly, to a bipolar transistor with an ultra small self-aligned polysilicon emitter and a method of forming the silicon germanium base of the transistor.
2. Description of the Related Art
A bipolar transistor is a three-terminal device that can, when properly biased, controllably vary the magnitude of the current that flows between two of the terminals. The three terminals include a base terminal, a collector terminal, and an emitter terminal. The charge carriers, which form the current, flow between the collector and the emitter terminals, while variations in the voltage on the base terminal cause the magnitude of the current to vary.
Due to the increasing speed of, and demand for, battery-powered devices, there is a need for a faster bipolar transistor that utilizes less power. Increased speed can be obtained by using a silicon germanium base. Lower power consumption can be obtained by reducing the maximum current that can flow between the two terminals.
One approach for reducing the maximum current is to reduce the size of the base-to-emitter junction, preferably to sub-lithographic feature sizes.
FIG. 1
shows a cross-sectional diagram that illustrates a portion of a prior-art bipolar transistor
100
that has a base-to-emitter junction with a sub-lithographic width.
As shown in
FIG. 1
, transistor
100
includes a collector layer
110
, a base layer
112
that is formed on collector layer
110
, and a field oxide region FOX that adjoins layer
112
. In addition, transistor
100
includes a thin oxide layer
114
that is formed on a portion of base layer
112
and the field oxide region FOX, and an n+ extrinsic emitter
116
that is formed on thin oxide layer
114
.
As further shown in
FIG. 1
, transistor
100
also includes an n+ intrinsic emitter region
118
that is formed in base layer
112
, and an n+ poly ridge
120
that is connected to extrinsic emitter
116
and n+ intrinsic emitter region
118
. Extrinsic emitter
116
, intrinsic emitter region
118
, and poly ridge
120
form the emitter of transistor
100
.
Transistor
100
additionally includes a base silicide contact
122
that is formed on base layer
112
, and an emitter silicide contact
124
that is formed on extrinsic emitter
116
. In addition, an oxide spacer
126
is formed on base layer
112
between poly ridge
120
and base contact
122
.
During fabrication, poly ridge
120
is formed to have a maximum width (measured laterally) that is smaller than the minimum feature size that is obtainable with a given photolithographic process. After poly ridge
120
has been formed, emitter region
118
is formed during an annealing step which causes dopants to outdiffuse from poly ridge
120
into base layer
112
.
As a result, a very small base-to-emitter junction results. A small base-to-emitter junction limits the magnitude of the current that can flow through transistor
100
. Reduced current, in turn, provides lowpower operation. (See “Poly Emitter Transistor (PRET): Simple Low Power Option to a Bipolar Process,” Wim van der Wel, et al., IEDM 93-453, 1993, pp. 17.6.1-17.6.4.)
One drawback of transistor
100
, however, is that transistor
100
. requires the added cost and complexity of a double polysilicon process (extrinsic emitter
116
is formed from a first polysilicon (poly-1) layers while poly ridge
120
is formed from a second polysilicon (poly-2) layer). In addition, emitter dopant diffusion into base
112
can be less, compared to a conventional single-poly device architecture, due to the possible presence of oxide at the poly1-to-poly2 interface (emitter
116
to poly ridge
120
interface).
Another drawback of transistor
100
is that, although
FIG. 1
shows oxide spacer
126
formed on poly ridge
120
, in actual practice it is difficult to form an oxide side-wall spacer on a sloped surface. Gaps can result which, in turn, can lead to an electrical short circuit between base layer
112
and extrinsic emitter
116
following the salicidiation process (the process that forms base suicide contact
122
and emitter silicide contact
124
). Silicide is not formed on oxide. Thus it is critical that a uniformly thick layer of oxide (spacer
126
) separate base layer
112
from extrinsic emitter
116
.
A further drawback of transistor
100
is that the slope of the end wall of extrinsic emitter
116
can effect the width of poly ridge
120
. Although
FIG. 1
shows extrinsic emitter
116
with a vertical end wall, in actual practice, the end wall is often non-vertical, and non-uniform across a wafer that has a number of bipolar transistors. This, in turn, can result in the bipolar transistors having varying performances.
An additional drawback of transistor
100
is that poly ridge
120
is formed around and in contact with each side wall of extrinsic emitter
116
. A plan view of extrinsic emitter
116
would show emitter
116
with a square or rectangular shape with poly ridge
120
surrounding emitter
116
. As a result, transistor
100
has a large base-to-emitter contact area and a high base-to-emitter capacitance.
The parent invention discloses a bipolar transistor that has a base and an ultra small self-aligned polysilicon emitter. The base, in turn, includes silicon and germanium. The parent invention also discloses a method of forming the transistor that includes a step of chemically-mechanically polishing the base material to limit the base material to a predefined window.
One drawback of this method is that the chemicals used in the chemical-mechanical polishing step could interact with, and change the characteristics of, the base material. One alternate approach to limiting the base material to a predefined window is to use a photo masking step. Although this approach is workable, additional photo masking steps are expensive.
The selective deposition of base material is another alternate approach. This process, however, is very complex and typically has poor process yields due to various manufacturing issues. Thus, there is a need for a method of forming a base without subjecting the base material to damaging chemicals.
SUMMARY OF THE INVENTION
The present invention provides a method of forming a bipolar transistor that protects the base material from chemical interactions that occur during a chemical-mechanical polishing step. The wafer has a buried layer and an epitaxial layer of a first conductivity type that is formed over the buried layer. The epitaxial layer has a smaller dopant concentration than the buried layer.
The method of the present invention includes the steps of forming a trench in the epitaxial layer, and forming a layer of base material on the epitaxial layer and the trench. The method also includes the step of forming a layer of base protection material on the layer of base material.
The method additionally includes the step of chemically mechanically polishing the layer of base protection material, the layer of base material, and the epitaxial layer until a top surface of the epitaxial layer and a top surface of the layer of base protection material are substantially coplanar.
The method further includes the steps of forming an isolation region on the layer of base material and the layer of base protection material, and removing a portion of the layer of base protection material to expose a portion of the layer of base material.
The present invention also includes a bipolar transistor that is formed on a wafer. The wafer has a buried layer and an epitaxial layer of a first conductivity type that is formed over the buried layer. The epitaxial layer has a top surface and a smaller dopant concentration than the buried layer.
The transistor includes an intrinsic base region of a second conductivity type that is formed on the epitaxial layer. The intrinsic base region includes silicon and germanium, and has a first top surface and a vertically spaced-apart second top surface. The transistor also has an isolation region formed o
Fourson George
National Semiconductor Corporation
Pickering Mark C.
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