Method of forming teos oxide and silicon nitride passivation lay

Details Method of forming teos oxide and silicon nitride passivation lay Method of forming teos oxide and silicon nitride passivation lay

1995-06-05

1998-09-22

Niebling, John

Fishing, trapping, and vermin destroying

437195, 437194, 437238, 437241, 437 50, H01L 2128

Patent

active

058113169

ABSTRACT:
Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel stopper regions over the principal surface portions below the element separating insulating film of the substrate by introducing an impurity into all the surface portions including the active regions and the inactive regions of the substrate after the first mask and the second mask have been removed.

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