Method of forming stacked capacitor

Details Method of forming stacked capacitor Method of forming stacked capacitor

1998-12-07

2000-09-26

Whitehead, Jr., Carl

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

438398, 438665, 438253, 438255, H01L 2120

Patent

active

061241822

ABSTRACT:
A method of forming a bottom storage node of a capacitor on a substrate is disclosed. The method comprises the steps of: forming a first insulating layer atop said substrate; patterning and etching through said first insulating layer until said substrate is reached to form a bitline contact opening; depositing a conducting layer into said bitline contact opening and atop said first insulating layer; patterning and etching said conducting layer to form a bitline; depositing a second insulating layer atop said bitline and said first insulating layer; depositing a nitride layer atop said second insulating layer; depositing a third insulating layer atop said nitride layer; patterning and etching said first insulating layer, said second insulating layer, said nitride layer, and said third insulating layer, stopping at said substrate, to form a first storage node contact opening; depositing an amorphous polysilicon layer into said first storage node contact opening and atop said third insulating layer; patterning and etching said amorphous polysilicon layer and said third insulating layer, stopping at said nitride layer, to form a second storage node contact opening; forming amorphous polysilicon sidewall spacers along sidewalls of said second storage node contact opening; and depositing hemispherical grain (HSG) polysilicon on said amorphous polysilicon layer and said amorphous polysilicon sidewall spacers.

REFERENCES:
patent: 5795805 (1998-08-01), Wu et al.
patent: 6037624 (2000-03-01), King
patent: 6040215 (2000-03-01), Takaishi
patent: 6043131 (2000-03-01), Yu

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