Method of forming solder bump terminals on semiconductor element

Radiation imagery chemistry: process – composition – or product th – Imaging affecting physical property of radiation sensitive... – Making electrical device

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

156643, 228180A, 427 89, 427 96, 357 67, 430314, 430329, 430330, H01L 2188

Patent

active

042738598

ABSTRACT:
An improved method of forming raised input/output (I/O) terminals on the top surfaces of semiconductor elements of a semiconductor wafer. After via openings are formed through the passivation layer of such elements at locations where the I/O terminals are to be formed, which openings provide access to the metalization layers of the elements photolithographic techniques using a layer of heat resistant photoresist which is laminated to the top surface of the wafer are used to form openings through the photoresist layer to provide access to the metalization layers through the vias. A barrier metal layer is deposited on the exposed surfaces of the photoresist, and the metalization layers, and passivation layer of the elements. The barrier metal layer overlying the photoresist and then the photoresist are stripped from the wafer. The same photolithographic techniques using the same heat resistant photoresist material are used to define openings surrounding the barrier metal lining the via openings. A layer of solder is then deposited on the wafer. The solder overlying the photoresist and then the photoresist are stripped from the wafer. The solder is heated until it reflows to form raised I/O terminals of the devices which terminals each will have a substantially spherical exposed surface.

REFERENCES:
patent: 4042954 (1977-08-01), Harris
patent: 4057659 (1977-11-01), Pammer et al.
patent: 4172907 (1979-10-01), Mones et al.
patent: 4182781 (1980-01-01), Hooper et al.
patent: 4188438 (1980-02-01), Burns
A. van der Drift et al., "Integrated Circuits with Leads on Flexible Tape", Solid State Technology/Feb. 1976, pp. 27-35.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method of forming solder bump terminals on semiconductor element does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of forming solder bump terminals on semiconductor element, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming solder bump terminals on semiconductor element will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-155906

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.