Method of forming silicon oxide layer and method of...

Details Method of forming silicon oxide layer and method of... Method of forming silicon oxide layer and method of...

1999-10-29

2002-01-08

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

C438S680000, C438S689000, C438S753000, C438S757000, C438S758000, C438S800000, C438S931000, C219S121430, C219S121440

Reexamination Certificate

active

06337292

ABSTRACT:

This application claims the benefit of Japanese Patent Application No. 1998-309237, filed on Oct. 29, 1998, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of forming silicon oxide layer and method of manufacturing thin film transistor (TFT) thereby, and more particularly, to a method of forming silicon oxide layer preferably used as a gate insulator and an interspacing insulator.
2. Discussion of the Related Art
A liquid crystal display device (LCD) has been used widely to be minimized, lightened, and thinned, for example, an active matrix LCD of a twisted nematic (TN) mode has been known as a display device which has a low driving voltage, a small electric power consumption, a high contrast, and a high image quality.
In the active matrix LCD, a pair of substrates are opposing each other by interposing a liquid crystal layer, and one substrate between them is an active matrix substrate which has a switching element driving a pixel in each pixel.
FIG. 13
is showing a TFT which is a switching element of the active matrix substrate, and more particularly, showing a top-gate TFT. As shown in the figure, in the TFT
50
, a semiconductive layer
52
is formed in an island type on a transparent substrate
51
, and an interspacing insulator
53
is formed to cover the semiconductive layer
52
on the transparent substrate
51
. In addition, contact holes
54
,
55
are formed in the interspacing insulator
53
, and source and drain electrodes
56
,
57
are formed to connect the semiconductive layer
52
through the contact holes
54
,
55
respectively.
Further, a passivation layer
58
is formed on the interspacing insulator
53
to cover the source and drain electrodes
56
,
57
, a contact hole
59
is formed in the passivation layer
58
, and a pixel electrode
60
is formed to connect to the drain electrode
57
through the contact hole
59
.
The semiconductive layer
52
comprises a source region
61
, a drain region
62
, and a channel region
63
between the source and drain regions
61
,
62
. And, the source electrode
56
is connected to the source region
61
and the drain electrode
57
is connected to the drain region
62
. A gate insulator
64
is formed on the channel region
63
of the semiconductive layer
52
, and a gate electrode
65
is formed on the gate insulator
64
.
As to the TFT
50
shown in the
FIG. 13
, generally, the semiconductive layer
52
includes amorphous silicon (a-Si) or poly silicon (Poly-Si), the source, drain, and gate electrodes
56
,
57
,
65
include conductive metals, and the pixel electrode
60
is formed as a transparent conductive layer of indium tin oxide (ITO).
The insulating layer such as the gate insulator
64
, the interspacing insulator
53
, and the like includes silicon oxide (SiO
2
) layer. In the TFT
50
, the electric charge induced on the channel region
63
is controlled by the electric field when a voltage is applied to the gate electrode
65
, which make the current flowing between the source and drain electrodes to be on or off. And then the TFT functions as a switching element.
As described above, while it is necessary an insulating layer such as the gate insulator, the interspacing insulator, and the like to the TFT, the capabilities required to the gate insulator and interspacing insulator are different from each other respectively.
The gate insulator is the best important element which affects on the electric characteristic of the TFT, for example a threshold voltage, and so on. Hence, as the material for the gate insulator, it is required that the characteristic is stable and the insulating pressure is good although the thickness of the insulating layer is thin.
On the other hand, the interspacing insulator maintains the insulation between the conductive layers by interposing between two different conductive layers as being between the gate and source electrodes, or between the gate and drain electrodes.
As shown in the
FIG. 13
, however, the interspacing insulator is formed according to the step of the gate electrode or semiconductive layer, so that if the step coverage of the interspacing insulator is bad, there is a problem that the insulating pressure at the steps is lowered. Therefore, it is required the interspacing insulator which has a good step coverage and particularly has a high insulating pressure at the steps.
To form the silicon oxide layer used in these insulating layers, it has been known to employ the plasma CVD using tetraethlyorthosilicate (TEOS) as the material gas. Since the silicon oxide layer of TEOS group has a good step coverage, it is suitable for the interspacing insulator. However, there are problems that the formation speed of the layer is slow, the insulating pressure is low, and so on, further it could not be used as the gate insulator. Moreover, TEOS is in a liquid state at room temperature, so that it is difficult to employ the CVD using the TEOS after vaporizing this, and there is also the matter of high costs.
In addition, to form the silicon oxide layer used in these insulating layers, it has been known to employ a plasma CVD using the mixing gas of monosilane (SiH
4
) and nitrous oxide (N
2
O) as the material gas. Regarding this silicon oxide layer, because the step coverage is too bad and there is a concern of generating cracks from the steps into the layer, it could be used to the gate insulator, but it is not suitable for the interspacing insulator.
As described above, as to the insulating layer in the TFT, since the capabilities required according to the uses such as the gate insulator, the interspacing insulator, and the like differ respectively, it is necessary to use the material of the insulating layer according to the uses. However in this case, because of the process limitation according to the material gas, the degree of freedom in the process is lowered and it becomes a bad manufacturing process with a small productivity.
Therefore, although the silicon oxide layer is formed by the plasma CVD using same material gas, it could be used without regard to the uses such as the gate insulator, the interspacing insulator, and the like, and then it is required for rationalizing of the manufacturing process.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a method of forming silicon oxide layer that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a method of forming a silicon oxide layer being used as a gate insulator and an interspacing insulator. The silicon oxide layer has good characteristics such as the insulating pressure or the step coverage, improving the yield of the TFT, having no problems of treatment or cost. And the other object of the present invention is to provide a method of manufacturing a TFT with using the silicon oxide layer.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the method of forming a silicon oxide layer comprises the steps of:
providing two frequency excitation plasma CVD device which comprises a first high frequency power supply, a high frequency electrode connected to the a first high frequency power supply, a matching box toward the high frequency electrode having a matching circuit obtaining a matching of impedance between the first high frequency power supply and high frequency electrode; a second high frequency power supply, a susceptor electrode connected to the second high frequency power supply opposing the high frequency

Affiliated with

Also associated with

Rating

Method of forming silicon oxide layer and method of... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of forming silicon oxide layer and method of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming silicon oxide layer and method of... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2867465