Method of forming silicon nitride layer directly on HSG...

Details Method of forming silicon nitride layer directly on HSG... Method of forming silicon nitride layer directly on HSG...

2000-02-17

2003-03-04

Nguyen, Tuan H. (Department: 2813)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

C438S253000, C438S381000, C438S396000

Reexamination Certificate

active

06528436

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the manufacture of semiconductor devices, and in particular to methods and apparatus for thin silicon nitride layers.
BACKGROUND OF THE INVENTION
Silicon nitride is commonly used in the manufacture of semiconductor devices. Silicon nitride is a useful diffusion barrier layer. For example, gate structures in transistors often use such layers to prevent diffusion between the bottom silicon layer and the top conducting layer, such as the metal interconnect layer. Similarly, thin silicon nitride layers are utilized in interconnects between underlying active device regions and the metallization layer. Most commonly, thin layers of silicon nitride are used in semiconductor memories.
Dynamic random access memories (DRAMs) are the most widely used form of semiconductor memory to date. DRAMs are composed of memory cell arrays and peripheral circuitry required for cell access and external input and output. Each memory cell array is formed of a plurality of memory cells for storing bits of data. Typical memory cells are formed of a capacitor, for storing electric charges and a transistor, for controlling charge and discharge of the capacitor. Of primary concern is maximizing the storage capacitance of each memory cell capacitor, particularly in light of the demand for 256 Mb DRAMs today and higher densities in the future without increasing the chip space required to form the cell. In fact, there is a need to decrease the chip space required to form each memory cell. The importance of high density DRAMs can not be overstated in today's competitive microelectronics market. Devices are becoming smaller, but they are required to provide much more performance.
One way to achieve greater capacitance per unit area is to roughen the surface of the capacitor plate, increasing the surface area. As can be seen from the following equation, the most important parameters involved in achieving maximum charge, Q, stored on the capacitor are the thickness of the dielectric layer (t
ox
), the area of the capacitor (A), and the dielectric constant (∈). The voltage applied to the gate is V
g
.
Q
=(∈·
A·V
g
)/
t
ox
Increasing the capacitor area by forming the storage capacitor in a trench shape etched in the substrate is well known in the art, as well as using a stacked capacitor structure. Stacked-type capacitors feature a major part of the capacitor extending over the gate electrode and field isolating film of the underlying transistor. Such structures are generally composed of a lower plate electrode (consisting of a base portion a standing wall portion), a capacitor dielectric film, and an upper plate electrode. Other complex topographical lower plate electrode configurations have also been used to maximize the capacitive area of a memory cell, such as fin-type, double-sided, and roughened lower plate electrode structures produced using hemispherical grain (HSG) polysilicon. In addition to increasing the capacitive surface area of a memory cell, as can be seen from the above equation, the capacitor dielectric film must be as thin as possible to maintain the maximum charge stored on the capacitor. However, it must also prevent direct electrical contact between the lower and upper electrodes.
In order to minimize the thickness of the cell dielectric layer and further increase the cell capacitance, silicon nitride is commonly used in such memories due to its superior qualities as compared to silicon oxide (another commonly used dielectric in semiconductor integrated circuit fabrication) at such thicknesses. At thicknesses of 100 angstroms or less, silicon oxide exhibits a high defect density. Silicon oxide is further undesirable for use in memory cells due to its comparatively low dielectric constant
While silicon nitride is superior to silicon oxide at thicknesses below 100 angstroms, silicon nitride also has problems of its own. Pinholes, extending throughout a silicon nitride layer, often lead to current leakage, which decreases capacitance and can further degrade devices over time, making them unreliable.
One prior solution to overcoming the pinhole problem is to form a plurality of silicon nitride layers in place of a single layer, chancing the occurrence that pinholes in adjacent layers will not be aligned, thus preventing current leakage. However, this technique is not reliable and its use is limited in today's devices due to the need to make devices as small as possible.
Another problem experienced with using thin layers of silicon nitride in memory cells is obtaining sufficient step coverage of lower electrodes in such cells. As manufacturers are increasing the surface area of the lower electrode to increase cell capacitance, step coverage of such structures is often insufficient, leading to current leakage. Such structures often comprise stacked capacitors, fin-type capacitors, trench capacitors and roughened, double-sided (or simply roughened) lower electrode surfaces, such as hemispherical grain (HSG) polysilicon. The complex topographies of these structures present step coverage problems as devices are scaled down in size. Silicon nitride's affinity for depositing on silicon in comparison to other surrounding materials, such as insulator materials, further complicates the step coverage problem when topographies are composed of heterogenous materials.
To date, deposition of silicon nitride films has occurred at temperatures of higher than approximately 700 degrees Celsius. A disadvantage of using such high processing temperatures is that it decreases the thermal budget allowed for device formation. Once a thermal budget is consumed, subsequent thermal treatments are likely to degrade device performance. Since many types of materials in semiconductor manufacturing require the use of high processing temperatures for their manufacture, it is critical to minimize consumption of the thermal budget where possible.
A further disadvantage of using such high temperatures is that it is hard to provide a controllable, repeatable deposition process due to the high deposition rate associated with such higher temperatures. It is desirable to deposit thin nitride films in a more controlled, repeatable manner to provide better step coverage of complex topographical structures.
There is a need for a method for forming thin silicon nitride films on complex topographies with a minimum consumption of the thermal budget. In particular, there is a need for forming thin silicon nitride films having sufficient step coverage on such complex topographies. To date, the problem of obtaining sufficient step coverage and uniformity on roughened surfaces in particular has not been resolved. The use of such a rough surface material, HSG polysilicon, is becoming more prevalent, but a method for forming uniform silicon nitride films on HSG has not been found. In addition to the above needs, there is a further need for forming thin silicon nitride films in a way which reduces resulting leaking current in associated devices.
SUMMARY OF THE INVENTION
Silicon nitride films, having thicknesses of 100 angstroms or less, are formed using chemical vapor deposition (CVD). Deposition pressure regimes, which are higher than many prior pressure regimes, are used to provide more uniform step coverage on complex topographies. When using higher pressure regimes, a lower processing temperature is used to beneficially decrease thermal budget consumption and to reduce the deposition rate for achieving a more repeatable and controllable process.
Silicon nitride films, which result in reduced leakage currents for associated devices, are produced in accordance with the method of this invention. By using this invention, a single silicon nitride film may be used in a device since fewer pinholes are present in the film due to the high pressure regime of this invention. Step coverage of complex topographical structures is also greatly improved using this invention. For the first time, the problem of obtaining uniform silicon nitride films on hemispherical grain (HSG

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