Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2001-12-27
2003-08-12
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S592000, C438S964000, C438S260000
Reexamination Certificate
active
06605520
ABSTRACT:
TECHNICAL FIELD
A method of forming a silicon-germanium (SiGe) film, and more particularly to, a method of forming a silicon-germanium (SiGe) film capable of improving the set-up and electrical characteristics of a gate structure by reducing the surface roughness of the silicon-germanium (SiGe) film is disclosed.
BACKGROUND
The silicon-germanium (SiGe) film is a polycrystal film in which silicon (Si) and germanium (Ge) are combined. In the silicon-germanium (SiGe) film, germanium (Ge) has a larger size than silicon (Si) and has a melting temperature of about 936° C. which is lower than that of silicon (Si). Therefore, the silicon-germanium (SiGe) film could be easily grown with polycrystalline even at a relatively low temperature ranging from about 450 to about 550° C. This silicon-germanium (SiGe) film has advantages that it can prevent a penetration phenomenon of boron (B) in P
+
-type polysilicon, reduce the resistance value of a polysilicon layer due to activated boron dopant and reduce a depletion phenomenon of polysilicon, and can be manufactured in a current process of manufacturing silicon. Thus, it is expected that the silicon-germanium (SiGe) film may be used as a gate electrode material of next-generation semiconductor devices.
However, there is a problem incorporating SiGe films into current processes. In silicon-germanium (SiGe) films, as germanium (Ge) has a larger grain size than silicon (Si), the surface of the silicon-germanium (SiGe) film is rougher than a silicon (Si) film in which germanium (Ge) is not present. Therefore, as the content of germanium (Ge) increases, the surface roughness of the silicon-germanium (SiGe) film increases. Thus, if the silicon-germanium (SiGe) film with a rough surface is used as a gate electrode, it adversely affects an electrical characteristics of a gate structure as well as the gate structure.
The degree of the surface roughness can be described by means of a micro-structure evolution rule. According to the micro-structure evolution rule, a film is grown by an island growth mechanism if the material characteristic is completely different in a crystal growth of the film. At this time, the nucleus creation density affects the size limit of growing grains. Thus, as the size of grain is larger, the roughness of the film is increased.
In order to obtain a flat surface in a polysilicon film containing a large quantity of germanium (Ge), it is important that the density of the nucleus density is initially increased to form a thin film with micro-crystallite. For this, a method of first forming a silicon seed layer on a gate oxide or for polishing a silicon source gas has been employed.
The method of forming the silicon seed layer includes forming amorphous silicon with a thickness ranging from about 10 to about 100 Å on the gate oxide. This allows the silicon-germanium (SiGe) film to be easily grown into crystalline without being island-grown on the same silicon surface. Thus, there is a disadvantage that the nucleus creating density of the seed layer could not be increased by the surface reaction of a low temperature though the seed layer can be simply formed by continuous process but the film itself is amorphous.
The method of polishing the silicon source gas includes forming silicon monomer to the degree that it is not deposited on the gate oxide by including a large quantity of carrier gas such as hydrogen (H
2
) and the like into silane (SiH
4
) before the silicon-germanium (SiGe) film is deposited. In case of forming the silicon-germanium (SiGe) film using this method, there is a disadvantage that stability with respect to uniformity control is lowered.
As such, a common problem in the above two methods is that the nucleus creating potential of the silicon-germanium (SiGe) film is low. The reason is that the silicon-germanium (SiGe) film is not micro-crystalline. In other words, the seeding efficiency of these methods can be lowered since it is not micro-crystalline. More particularly, nucleus creation is advantageous in crystalline the interface energy of which is relatively low.
SUMMARY OF THE DISCLOSURE
A method of forming a silicon-germanium (SiGe) film capable of improving set-up and electrical characteristics of a gate structure by reducing the surface roughness of the silicon-germanium (SiGe) film is disclosed.
A method of forming a silicon-germanium (SiGe) film is disclosed which is characterized in that it comprises the steps of: fixing a semiconductor substrate in which a gate oxide is formed, within a deposition chamber; flowing SiH
4
and H
2
into said deposition chamber and forming silicon micro-crystallite on the surface of said gate oxide using a plasma system; and flowing SiH
4
, GeH
4
and H
2
into said deposition chamber to deposit silicon-germanium around a plurality of the silicon micro-crystallite.
Also, a method of forming a silicon-germanium (SiGe) film is disclosed which is characterized in that it comprises the steps of: fixing a semiconductor substrate in which a gate oxide is formed, within a deposition chamber; flowing SiH
4
and H
2
into said deposition chamber and forming silicon micro-crystallite on the surface of said gate oxide using a lot of thermal electrons emitted from a filament; and flowing SiH
4
, GeH
4
and H
2
into said deposition chamber to deposit silicon-germanium around a plurality of the silicon micro-crystallite.
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patent: 6060743 (2000-05-01), Sugiyama et al.
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patent: 6297095 (2001-10-01), Muralidhar et al.
patent: 6410412 (2002-06-01), Taira et al.
patent: 6413819 (2002-07-01), Zafar et al.
Booth Richard
Hynix Semiconductor Inc
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