Method of forming silicide layers over a plurality of...

Details Method of forming silicide layers over a plurality of... Method of forming silicide layers over a plurality of...

2002-07-02

2004-09-07

Nguyen, Van Thu (Department: 2824)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S682000, C438S685000

Reexamination Certificate

active

06787464

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to methods of forming silicide regions on transistors based upon gate critical dimensions.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate insulation thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors.
FIG. 1
depicts an example of an illustrative transistor
10
fabricated on an illustrative substrate
11
comprised of, for example, silicon. The transistor
10
is comprised of a gate insulation layer
14
, a gate electrode
16
, sidewall spacers
19
, and source/drain regions
18
. The gate electrode
16
has a critical dimension
16
A that approximately corresponds to the gate length of the transistor
10
. A plurality of trench isolation regions
17
are formed in the substrate
11
to electrically isolate the transistor
10
from other transistors (not shown) or structures. Also depicted in
FIG. 1
are a plurality of conductive contacts
20
formed in a layer of insulating material
21
. The conductive contacts
20
provide electrical connection to the source/drain regions
18
. As constructed, the transistor
10
defines a channel region
12
in the substrate
11
beneath the gate insulating layer
14
. The transistor
10
further comprises a plurality of metal silicide regions
13
formed above the gate electrode
16
and source/drain regions
18
.
The metal silicide regions
13
may be formed by depositing a layer of refractory metal (not shown), e.g., nickel, cobalt, titanium, platinum, erbium, tantalum, etc., above the source/drain regions
18
, the sidewall spacers
19
and the gate electrode
16
. Thereafter, a two-step heating process may be performed to convert the portions of the layer of refractory metal in contact with the gate electrode
16
and the source/drain regions
18
into a metal silicide, e.g., nickel silicide, cobalt silicide, etc. Such silicide regions
13
are formed for a variety of purposes, e.g., to reduce the contact resistance for the source/drain regions
18
and gate electrode
16
. The metal silicide regions
13
may, at least in some cases, assist in increasing device performance in that they tend to reduce various resistances encountered in operating the transistor
10
.
During the process of forming such metal silicide regions
13
, a volumetric amount of the polysilicon gate electrode
16
is consumed. The volumetric amount of the gate electrode
16
consumed depends, at least in part, on the thickness of the layer of refractory metal deposited on the partially completed transistor and on the critical dimension
16
A of the gate electrode
16
.
To combat this problem, the thickness of the layer of refractory metal is controlled based upon the smallest critical dimension
16
A of the gate electrode structures
16
for one or more of the transistors
10
formed above the substrate
11
. However, using such processing techniques leads to other problems. For example, depositing the layer of refractory metal to the very small thickness determined based upon the smallest critical dimension
16
A may be very difficult to accomplish due to the thinness of the layer of refractory metal. Additionally, forming the metal silicide regions
13
using this technique will cause all of the metal silicide regions
13
formed on a wafer to be formed to a thickness that is less than desirable for at least some of the transistors
10
formed on the substrate. That is, all other things being equal, it may be desirable that the metal silicide regions
13
on the gate electrode
16
of at least some transistors
10
be thicker than that dictated by the smallest gate critical dimensions
16
A on the substrate. As a result, the electrical characteristics of some of the transistors
10
, and products incorporating such transistors, may be adversely impacted due to the use of excessively thin metal silicide regions
13
on all of the transistors
10
formed above a substrate
11
.
The present invention is directed to a device and various methods that may solve, or at least reduce, some or all of the aforementioned problems.
SUMMARY OF THE INVENTION
The present invention is generally directed to various methods of forming metal silicide regions on transistors based upon gate critical dimensions. In one illustrative embodiment, the method comprises forming a layer of refractory metal above a plurality of transistors, reducing a thickness of a portion of the layer of refractory metal above at least some of the transistors and performing at least one anneal process to form metal silicide regions above the transistors. In another illustrative embodiment, the method comprises forming a layer of refractory metal above the plurality of transistors, reducing the thickness of the layer of refractory metal above at least a first of the transistors having a gate electrode with a critical dimension that is less than a critical dimension of a gate electrode structure of another of the plurality of transistors, and performing at least one anneal process to form metal silicide regions on the plurality of transistors. In yet another illustrative embodiment, the method comprises forming a layer of refractory metal to an original thickness above a plurality of transistors, reducing the original thickness of a portion of the layer of refractory metal above at least some of the transistors to define a layer of refractory metal having multiple thicknesses, and performing at least one anneal process to convert portions of the layer of refractory metal having multiple thicknesses to metal silicide regions on the transistors.
In a further illustrative embodiment, the method comprises forming a plurality of transistors above a semiconducting substrate, a first of the transistors having a gate electrode with a critical dimension that is less than a critical dimension of a gate electrode structure of another of the plurality of transistors, forming a layer of refractory metal above the plurality of transistors, forming a patterned masking layer above the layer of refractory metal, the patterned masking layer exposing at least a portion of the layer of refractory metal formed above the first transistor, performing an etching process on the exposed portion of the layer of refractory metal to reduce the original thickness of the exposed portion of the layer of refractory metal to a second thickness, and performing at least one anneal process on the layer of refractory metal after the etching process is performed to form metal silicide regions on the plurality of transistors. In yet a further illustrative embodiment, the method comprises forming a plurality of transistors above a semiconducting substrate, identifying a first group of the transistors with gate electrodes of a critical dimension that is less than a critical dimension of gate electrodes of a second group of transistors of the plurality of transistors, identifying at least one region of the substrate wherein the first group of transistors are located, forming a layer of refractory metal above the plurality of transistors, performing an etching process to reduce a thickness of the layer of refractory metal in the identified at least

Affiliated with

Also associated with

Rating

Method of forming silicide layers over a plurality of... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of forming silicide layers over a plurality of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming silicide layers over a plurality of... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3262006