Method of forming silicide gate with interlayer

Details Method of forming silicide gate with interlayer Method of forming silicide gate with interlayer

2006-07-11

2008-09-30

Sefer, A. (Department: 2826)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C257SE21203

Reexamination Certificate

active

07429526

ABSTRACT:
A field-effect transistor (“FET”) or similar device has a fully silicided (“FUSI”) gate electrode. The gate electrode has a gate interface silicide portion between the gate dielectric and a bulk gate silicide portion. The gate interface silicide is formed by depositing a gate electrode interface layer having silicide retardation species underneath the metal/silicon layers used to form the gate silicide. The gate electrode interface layer retards silicide formation at the gate dielectric/gate electrode interface when the bulk gate silicide is formed, and the gate interface silicide is then formed at a higher temperature or longer heat cycle time.

REFERENCES:
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R. A. Donaton et al.; “Co silicide formation on SiGeC/Si and SiGe/Si layers”; Appl. Phys. Lett. 70 (10); Mar. 10, 1997; 1997 American Institute of Physics, pp. 1266-1268.

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