Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Self-aligned
Reexamination Certificate
2001-01-29
2003-03-04
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Self-aligned
C438S480000
Reexamination Certificate
active
06528381
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of forming a silicide, more particularly, to a method of forming Co silicide or salicide which provides an excellent p-type gate conductivity in dual gates consisting of fine grains for CMOS devices by increasing grain size in the p-type gate. The p-type gate is then re-doped with n-type impurities such as As or the like having a characteristic of increasing grain sizes within a critical dose, and which also reduces sheet resistance by securing thermal stability in following processing steps.
2. Discussion of Related Art
In an ultra highly integrated semiconductor device, the widths of impurity regions and gates are decreased. Thus, operation speed is reduced because contact resistance of the impurity region and sheet resistance of the gate are increased.
The contact and sheet resistances may be reduced by forming silicide layers on a gate electrode of doped polysilicon, or by forming electrodes of a semiconductor device with a low resistance substance such as Al alloy, W, or the like. In this case, another silicide layer may be formed on surfaces of the impurity regions as soon as the silicide layer is formed on the gate electrode of doped polysilicon. This is called a salicide structure which decreases contact resistance.
As mentioned above, the relatively high resistance of a gate is the major factor of reducing the operation speed of a semiconductor device because a design rule for a semiconductor device becomes more strict.
A line width or a critical dimension is scaled down to submicron range to improve operational characteristics and improve the degree of integration in semiconductor integrated circuits. This reduces spaces between adjacent gate lines of MOS transistors in the semiconductor integrated circuit. Naturally, parasitic capacitance among the gate lines increases greatly, thereby lowering the signal transferring speed of the circuit.
In such a semiconductor integrated circuit, the signal transferring speed is affected by a delay time, which depends on a line resistance R of a gate line and a parasitic capacitance C among gate lines.
Therefore, the line resistance or the parasitic capacitance is decreased by increasing an interval between the gate lines in order to improve the signal transferring speed of a circuit.
Unfortunately, it is hard to increase the degree of integration when increasing the spacing between the gate lines. Therefore, the delay time of a signal is instead reduced by decreasing the line resistance of the gate. In order to reduce the line resistance of the gate, a gate having a polycide structure is formed in which silicide is stacked on heavily doped polysilicon.
Fabricating a gate electrode having low resistance is essential to improve the operation speed of a device. For such improvement, a gate electrode of refractory metal silicide (with a low specific resistance) is fabricated. Such a gate electrode having has a polycide (silicide on doped polysilicon) structure.
Although WSi
2
is frequently used in the polycide structure, some silicide having a lower resistance is required for the reduced area occupied by a unit device because of the increased integration of the device. Besides, the specific resistance of WSi
2
is 60 to 200 &mgr;&OHgr;-cm. Therefore, CoSi
2
or TiSi
2
having a specific resistance of 15 to 20 &mgr;&OHgr;-cm meets this requirement.
Methods of forming a polycide structure may be divided into two categories. First, silicide may be formed by depositing a metal layer on a doped polysilicon and by reacting the metal with the doped polysilicon in a thermal treatment. In this case, the resultant polycide, which is relatively thick, fails to form a thick and uniform silicide layer.
Generally, the reaction between pure metal and silicon is very vigorous, creating a rough morphology at the interface between silicide and silicon. Therefore, it is hard to pattern a gate electrode precisely. This phenomenom is disclosed in detail in, for example, [J.S. Byun et al. J. Electrochem. Soc., vol.144,3175(1997)].
Moreover, when fine-grained polysilicon is used to permit sufficient doping, the vigorous reaction between the doped polysilicon of which grain boundaries are much enhanced and the heavily-doping dopants fails to form an uniform polycide structure.
Second, there is a method forming polycide by depositing a silicide substance directly on a doped polysilicon, instead of reacting metal and silicon in a thermal treatment. Generally, a sputtering method is used to form a silicide layer on a doped polysilicon layer using a silicide composite target.
Unfortunately, this method lessens the reliability of a resultant semiconductor device due to particles generated from forming silicide as the integration degree of a device increases. Specifically, the sputtering rates of the respective elements in the composite target consisting of metal and silicon differ from each other, which prevents formation of a silicide layer having an uniform composition and causes the generation of particles.
As a CMOS transistor becomes highly integrated and sizes of NMOS and PMOS transistors are reduced accordingly, short channel effect and hot carriers ruin the characteristics of a device. Hence, the degradation of the NMOS and PMOS transistors is prevented by using an LDD(lightly doped drain) structure.
Gates of the NMOS and PMOS transistors of a CMOS device are heavily doped with n-type impurities commonly. Accordingly, a channel of the PMOS transistor is not formed in a top surface of a substrate but formed in a bulk of the substrate, thereby lowering breakdown voltage of the transistor due to punch through.
Therefore, a dual-gate CMOS transistor device is conventionally available in which a PMOS transistor has a heavily-doped gate doped with p-type impurities whereas the other gate of an NMOS transistor is heavily doped with n-type impurities. The channel of the PMOS transistor in such a dual-gate CMOS device is formed in a top surface of a substrate, thereby preventing the decrease of breakdown voltage due to punch-through.
The dual-gate CMOS transistor prevents a lowering of the signal transferring speed because of the increased integration of a device by reducing sheet resistance by forming a polycide gate structure consisting of heavily doped polysilicon and suicide.
Although very fine-grained polysilicon is required for doping a gate sufficiently because of scaling-down, thermal stability of silicide of CoSi
x
or the like of such polysilicon constitution is very poor because of the grain sizes participating directly in the silicidation reaction with Co.
Namely, silicidation occurs abruptly since the total surface area of the polysilicon grains is increased. Abrupt silicidation causes metal agglomeration in a subsequent thermal treatment, thereby drastically increasing sheet resistance.
FIG. 1A
to
FIG. 1D
illustrate a method of forming silicide in a semiconductor device, in particular cross-sectional views of a dual-gate CMOS transistor device according to a related art.
Referring to
FIG. 1A
, an n-well
11
and a p-well
12
are formed in predetermined portions of a semiconductor substrate
20
by doping the substrate selectively with n and p-type impurities, respectively.
A field oxide layer
13
electrically isolating unit devices is formed at a boundary between the n- and p-wells
11
and
12
by, for example, LOCOS (Local Oxidation of Silicon) or STI (shallow trench isolation). A gate insulating layer
14
is formed by thermally oxidizing surfaces of the n-and p-wells
11
and
12
.
A silicon layer
15
is then formed on the field oxide layer
13
and the gate insulating layer
14
by depositing undoped polysilicon or amorphous silicon by chemical vapor deposition(hereinafter abbreviated CVD). If amorphous silicon is deposited, the amorphous silicon is transformed into polycrystalline silicon by a thermal treatment. In this case, the silicon layer
15
consisting of polycrystallites is made of fine grains to facilitate impurity doping to
Ahn Jae-Gyung
Lee Key-Min
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