Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2002-09-10
2004-08-31
Le, Vu A. (Department: 2824)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S435000
Reexamination Certificate
active
06784075
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the manufacture of semiconductor devices, and more particularly to a method of forming shallow trench isolations in a semiconductor substrate to reduce stresses caused by etching shallow trenches.
2. Description of the Related Art
In the integrated circuit (IC) industry, shallow trench isolation (STI) is replacing conventional local oxidation of silicon (LOCOS) in order to form improved field isolation structures. The basic STI technology involves etching of the semiconductor substrate to form trenches and then refilling the trenches with an insulating material to produce an isolation region followed by planarization of the insulating material by chemical mechanical polishing (CMP). The steps mentioned above may cause mechanical or thermal stresses in the active semiconductor substrate. These stresses are believed to cause dislocations or defect sites in the active substrate. Accordingly, it has been found that a high leakage current path exists along the source and drain regions of a transistor device formed during subsequent steps in the semiconductor substrate, thereby rendering a lower yield.
U.S. Pat. No. 6,350,662 to Thei et al. discloses a method to reduce defects in shallow trench isolation using nitrogen annealing for 30 to 150 minutes. Defects, dislocations, interface traps, and stresses in the semiconductor substrate can be reduced or eliminated.
U.S. Pat. Nos. 5,780,346 and 6,261,925 to Arghavani at al. disclose a method of forming an isolation structure in a semiconductor substrate. A trench is first etched into a semiconductor substrate. A first oxide layer is then formed in the trench. The first oxide layer is subjected to a nitrogen-oxide gas ambient and is annealed to form an oxy-nitride interface between the first oxide and the semiconductor substrate. However, the silicon oxynitride is formed by nitridation of the silicon oxide layer at an elevated temperature. Process complexity and manufacturing cost may be increased.
Therefore, a need has arisen for a method of forming shallow trench isolation in a semiconductor substrate that can eliminate or reduce stresses caused by bombardment during reactive ion etching for the shallow trench.
SUMMARY OF THE INVENTION
In view of the above disadvantages, an object of the invention is to provide a method of forming shallow trench isolations in a semiconductor substrate. This method is capable of reducing or eliminating the main stresses.
A further object of the invention is to reduce the process complexity and manufacturing cost.
In accordance with one aspect of the invention, there is provided a method of forming shallow trench isolation in a semiconductor substrate. A hard mask having an opening is formed on the semiconductor substrate. The semiconductor substrate is etched through the opening to form a shallow trench. The semiconductor substrate, such as silicon substrate, is annealed in an ambient containing nitric oxide or nitrogen and oxygen to form a silicon oxynitride film on the shallow trench to serve as a barrier to prevent dopants from source/drain outdiffusion. Oxidation and nitridation occur on the exposed silicon substrate in the annealing step. An insulator is then formed on the hard mask to fill the shallow trench. The insulator is planarized while the hard mask is used as the polishing stop layer. Thereafter, the hard mask is removed to expose the upper surface of the semiconductor substrate and leave a shallow trench isolation.
The semiconductor substrate is preferably annealed after the semiconductor substrate is pre-cleaned by a standard clean solution such as a diluted NH
4
OH/H
2
O
2
solution (known as “SC1”) or diluted NH
4
OH/HCl solution (SC2) followed by cleaning the semiconductor substrate with deionized water.
Furthermore, the semiconductor substrate is preferably annealed at 800 to 1100° C. in an ambient containing nitric oxide or nitrogen and oxygen gas for 2 to 15 minutes.
In accordance with another aspect of the invention, the hard mask preferably comprises a thermal pad oxide formed on the upper surface of the semiconductor substrate and a pad nitride deposited on the pad oxide.
In accordance with a further aspect of the invention, the shallow trench is preferably performed by anisotropic etching using a reactive gas containing HBr, Cl, and CF
4
.
In accordance with yet another aspect of the invention, the insulator is preferably silicon oxide deposited by high-density plasma chemical vapor deposition (HDPCVD).
In accordance with a still further aspect of the invention, the insulator is planarized by chemical mechanical polishing or etching back until the upper surfaces of the semiconductor substrate and the hard mask are approximately coplanar.
REFERENCES:
patent: 5763315 (1998-06-01), Benedict et al.
patent: 5780346 (1998-07-01), Arghavani et al.
patent: 6153480 (2000-11-01), Arghavani et al.
patent: 6165854 (2000-12-01), Wu
patent: 6261925 (2001-07-01), Arghavani et al.
patent: 6323106 (2001-11-01), Huang et al.
patent: 6333232 (2001-12-01), Kunikiyo
patent: 6350662 (2002-02-01), Thei et al.
patent: 6403428 (2002-06-01), Jeng
patent: 2002/0068415 (2002-06-01), Tseng et al.
patent: 2002/0177270 (2002-11-01), Beyer et al.
patent: 2002/0197886 (2002-12-01), Niimi et al.
patent: 2003/0015736 (2003-01-01), Beyer et al.
patent: 2003/0203515 (2003-10-01), Lin et al.
Huang Chian-Kai
Ku Tzu-Kun
Le Vu A.
Owens Beth E.
Silicon Integrated Systems Corp.
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