Method of forming shallow trench isolation regions in...

Details Method of forming shallow trench isolation regions in... Method of forming shallow trench isolation regions in...

2011-01-18

2011-01-18

Toledo, Fernando L (Department: 2895)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S424000, C438S426000, C257SE21546

Reexamination Certificate

active

07871897

ABSTRACT:
A mask pattern is formed on a semiconductor substrate in which a cell region, a PMOS region, and an NMOS region are defined. Trenches are formed in the cell region, the PMOS region, and the NMOS region. A sidewall oxide layer and a protection layer are formed in the trenches, and a portion of the protection layer in the PMOS region is removed. A first device isolation insulating layer is formed on the substrate, filling the trenches. Portions of the first device isolation insulating layer are removed to expose the mask pattern and the trenches of the cell region and the NMOS region and to leave a portion of the first device isolation insulating layer in the trench in the PMOS region. A liner is formed on the portion of the first device isolation region in the trench in the PMOS region and conforming to sidewalls of the trenches in the cell region and the NMOS region. A second device isolation insulating layer is formed on the substrate, filling the trenches in the cell region and the NMOS region. Portions of the second device isolation insulating layer are removed to expose the mask pattern and to leave portions of the second device isolation insulating layer in the trenches of the cell region and the NMOS region.

REFERENCES:
patent: 7033907 (2006-04-01), Kim
patent: 2008/0138958 (2008-06-01), Lee
patent: 2009/0256233 (2009-10-01), Eun
patent: 2004 063591 (2004-02-01), None
patent: 2006 286889 (2006-10-01), None
patent: 1020070058116 (2007-06-01), None

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