Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2002-09-10
2004-04-13
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S437000, C438S692000
Reexamination Certificate
active
06720235
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the manufacture of semiconductor devices, and more particularly to a method of forming shallow trench isolation in a semiconductor substrate to reduce stress caused by etching for shallow trench.
2. Description of the Related Art
In the integrated circuit (IC) industry, shallow trench isolation (STI) is replacing conventional local oxidation of silicon (LOCOS) in order to form improved field isolation structure. The basic STI technology involves etching of the semiconductor substrate to form trenches and then refilling the trenches with an insulating material to produce an isolation region followed by planarization of the insulating material by chemical mechanical polishing (CMP). The steps mentioned above may cause mechanical or thermal stress in the active semiconductor substrate. These stress are believed to cause dislocations or defect sites in the active substrate. Accordingly, it has been found that there exists a high leakage current path along the source and drain regions of a transistor device formed during subsequent steps in the semiconductor substrate, thereby rendering a lower yield.
U.S. Pat. No. 6,350,662 to Thei et al. discloses a method of reducing defects in shallow trench isolation using nitrogen annealing for 30 to 150 minutes. Defects, dislocations, interface traps, and stress in the semiconductor substrate can be reduced or eliminated.
However, silicon nitride may be generated in the semiconductor substrate during nitrogen annealing, affecting ion implantation for well regions and source/drain regions in the subsequent steps.
Therefore, a need has arisen for a method of forming shallow trench isolation in a semiconductor substrate that can eliminate or reduce stress caused by bombardment during reactive ion etching for the shallow trench.
SUMMARY OF THE INVENTION
In view of the above disadvantages, an object of the invention is to provide a method of forming shallow trench isolation in a semiconductor substrate. This method is capable of reducing or eliminating stress.
A further object of the invention is to improve the semiconductor device performance.
A further object of the invention is to prevent formation of silicon nitride in the semiconductor substrate caused by the nitrogen annealing mentioned above.
In accordance with one aspect of the invention, there is provided a method of forming shallow trench isolation in a semiconductor substrate. A hard mask having an opening is formed on the semiconductor substrate. The semiconductor substrate is etched through the opening to form a shallow trench. The semiconductor substrate is annealed in an ambient containing argon gas. An insulator is then formed on the hard mask to fill the shallow trench. The insulator is planarized while the hard mask is used as the polishing stop layer. Thereafter, the hard mask is removed to expose the upper surface of the semiconductor substrate and leave a shallow trench isolation.
The semiconductor substrate is preferably annealed after the semiconductor substrate is pre-cleaned by a standard clean solution such as a diluted NH
4
OH/H
2
O
2
solution (known as “SC1”) or diluted NH
4
OH/HCl solution (SC2) followed by cleaning the semiconductor substrate with deionized water.
Furthermore, the semiconductor substrate is preferably annealed at 1150 to 1200° C. in an ambient containing argon gas for 1 to 2 hours.
In accordance with another aspect of the invention, there is provided a method of forming shallow trench isolation in a semiconductor substrate, preferably silicon substrate. The hard mask preferably comprises a thermal pad oxide formed on the upper surface of the semiconductor substrate and a pad nitride deposited on the pad oxide.
In accordance with a further aspect of the invention, there is provided a method of forming shallow trench isolation in a semiconductor substrate. The shallow trench is preferably formed by anisotropic etching using a reactive gas containing HBr, Cl, and CF
4
.
In accordance with yet another aspect of the invention, the insulator is preferably silicon oxide deposited by high-density plasma chemical vapor deposition (HDPCVD). If necessary, a liner oxide and/or liner nitride is conformally formed on the interior surface of the shallow trench before formation of the insulator deposited by HDPCVD.
In accordance with a still further aspect of the invention, there is provided a method of forming shallow trench isolation in a semiconductor substrate. The insulator is planarized by chemical mechanical polishing or etching back until the upper surfaces of the semiconductor substrate and the hard mask are approximately coplanar.
According to the method of the invention, the semiconductor substrate near the shallow trench has no undesirable silicon nitride thus improving the semiconductor device performance.
REFERENCES:
patent: 6083808 (2000-07-01), Shin et al.
patent: 6350662 (2002-02-01), Thei et al.
patent: 6461950 (2002-10-01), Yin et al.
Ghandhi, S. VLSI Fabrication Principles, John Wiley and Sons, Inc. p. 518, 1983.*
Wolf, S., et al., Silicon Processing for the VLSI Era:Process Technology, Lattice Press, p. 534.
Huang Chian-Kai
Ku Tzu-Kun
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