Method of forming shallow trench isolation

Details Method of forming shallow trench isolation Method of forming shallow trench isolation

2000-03-20

2001-03-27

Dang, Trung (Department: 2823)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S424000, C438S437000, C148SDIG005

Reexamination Certificate

active

06207535

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 89101070, filed Jan. 24, 2000.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of fabricating shallow trench isolations (STI). More particularly, the present invention relates to a method of fabricating the STI, which method solves the problems of microscratch and dislocation.
2. Description of Related Art
Implementing electric circuits involves connecting isolated devices through specific electrical paths, it is therefore be possible to isolate devices built into the silicon from one another when fabricating silicon integrated circuits. With advent of integrated circuits, it became necessary to provide electrical isolation between the devices fabricated on the same piece of silicon. One of the most important techniques developed conventionally for latchup protection was termed local oxidation of silicon (LOCOS) isolation, which involved the formation of a semirecessed oxide in the nonactive areas of the substrate.
As device geometries reached submicron size, conventional LOCOS isolation technologies reached the limits of their effectiveness, and alternative isolation processes were needed. Newer approach, such as shallow trench isolation, where shallow, refilled trenches are used primarily for isolating devices of the same type, is adopted to overcome some drawbacks of conventional LOCOS for small-geometry devices.
FIGS. 1A and 1B
are cross-sectional views of two conventional STI structures refilled with different oxide layers. Referring to
FIG. 1A
, a buried-oxide (BOX) isolation technology is adopted to form a conventional STI. A substrate
100
a
is provided with a pad oxide layer
102
a
and a silicon nitride layer
104
a
formed thereon, wherein the pad oxide layer
102
a
serves to cushion the transition of stresses between the substrate
100
a
and the silicon nitride layer
104
a.
Active regions (not shown) on the substrate
100
a
are defined with a photolithographic step, followed by etching a part of the pad oxide layer
102
a
and silicon nitride layer
104
a
to form openings (not shown). The openings are then over-etched to form trenches
106
a
in the substrate
100
a,
and the trenches
106
a
are refilled by forming a layer of silicon oxide
108
a
globally on the silicon nitride layer
104
a.
The method for forming the silicon oxide layer
108
a
includes chemical vapor deposition (CVD). The silicon oxide layer
108
a
is then planarized by chemical mechanical polishing (CMP), so that a part of the silicon oxide layer
108
a
is removed until the silicon nitride layer
104
a
is exposed. However, particles in the CMP slurry can damage the surface of the silicon oxide layer
108
a,
causing defects known as microscratches after CMP is performed. Furthermore, a portion of the silicon oxide layer
108
a
is lost during a cleaning step, thus creating problem to control the profile of the STI.
A method to densify the silicon oxide layer was then suggested to solve the problem mentioned above and it is best illustrated in FIG.
1
B. Accordingly, the conventional method for forming the silicon oxide layer is modified to solve the problem of microscratches resulted from CMP. From the diagram, an additional thermal treatment, such as thermal annealing, is performed to the silicon oxide layer so as to harden the silicon oxide layer
108
b.
Inevitably, there are also problems associated with this annealing technique as a harder silicon oxide layer creates stresses at the bottom of the STI. The stresses cause dislocations by compressing or distending a crystalline lattice of the substrate
100
b,
while the dislocations can interact with each other to affect the mechanical and electrical characteristics of the STI.
SUMMARY OF THE INVENTION
The invention provides a method of fabricating shallow trench isolations (STI), which method provides a substrate with a first oxide layer and a silicon nitride layer formed thereon. The first oxide layer and the silicon nitride layer are patterned to define active areas and form openings. The openings are then over etched to form trenches for fabricating the STI, followed by forming a second oxide layer that conforms to a profile of the trenches. A third oxide layer is globally formed to cover the second oxide layer, sidewalls of the first oxide layer, and the silicon nitride layer. A thermal process is performed to densify a portion of the third oxide layer, so that a top portion of the third oxide layer is harder than a lower portion of the third oxide layer. The excessive portion of the third oxide layer above the silicon nitride layer is removed by performing chemical mechanical polishing (CMP), which planarizes a top surface of the third oxide layer.
As embodied and broadly described herein, the invention provides a fabrication method of the STI, which forms the third oxide layer with a harder top portion and a softer lower portion. The method for forming the third oxide layer includes forming the third oxide layer by atmospheric pressure chemical vapor deposition (APCVD), performing a thermal annealing to the third oxide layer, and planarizing the third oxide layer. The top portion in this case is defined as a portion of the oxide layer higher than the second oxide layer, while the lower portion is defined as a portion of the oxide layer lower than the first oxide layer. Since the third oxide layer is a double layered structure having two different densities. The harder top portion of the third oxide layer can withstand any damage from CMP slurry when CMP is performed to planarize the surface of the third oxide layer. The softer lower portion of the third oxide layer, on the other hand, does not create stresses at the bottom of the STI, and thus does not produce dislocations that would affect the mechanical and electrical characteristics of the STI.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5786262 (2000-08-01), Jang et al.
patent: 5885883 (1999-03-01), Park et al.
patent: 5960299 (1999-09-01), Yew et al.
patent: 6033970 (2000-03-01), Park
patent: 6096622 (2000-08-01), Kim et al.
patent: 959496 (1999-11-01), None

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