Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1996-11-06
1998-06-02
Niebling, John
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438637, 438643, 438648, 438650, 438672, 438687, H01L 2128
Patent
active
057599157
ABSTRACT:
The present invention provides a semiconductor device including an improved buried electrode formed by selective CVD. In this semiconductor device, a first insulation layer is formed on a semiconductor substrate. A first conductive layer is formed along an inner surface of a recess of an opening formed on the first insulation layer. A second conductive layer is formed on the first conductive layer in the recess of the opening. The second conductive layer is flush with the first insulation layer. The surfaces of the first and second conductive layers are coated with a third conductive layer. A second insulation layer is formed on the first insulation layer and the third conductive layer. A via hole is formed through the second insulation layer and the third conductive layer and reaches to the second conductive layer. A buried electrode layer is grown in the via hole and formed in contact with the second conductive layer. A fourth insulation layer has a group of conductive layers formed on the second insulation layer and the buried electrode layer and electrically connected to the second conductive layer through the buried electrode layer formed in the via hole.
REFERENCES:
patent: 5231053 (1993-07-01), Bost et al.
patent: 5289035 (1994-02-01), Bost et al.
patent: 5313100 (1994-05-01), Ishii et al.
patent: 5341026 (1994-08-01), Harada et al.
patent: 5355020 (1994-10-01), Lee et al.
patent: 5380679 (1995-01-01), Kano
patent: 5385868 (1995-01-01), Chao et al.
patent: 5404029 (1995-04-01), Husher et al.
patent: 5444022 (1995-08-01), Gardner
patent: 5486492 (1996-01-01), Yamamoto et al.
patent: 5529954 (1996-06-01), Iijima et al.
patent: 5563099 (1996-10-01), Grass
Matsunaga Noriaki
Matsuno Tadashi
Shibata Hideki
Usui Takamasa
Bilodeau Thomas G.
Kabushiki Kaisha Toshiba
Niebling John
LandOfFree
Method of forming semiconductor device having an improved buried does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of forming semiconductor device having an improved buried, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming semiconductor device having an improved buried will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1459215