Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Patent
1998-05-28
2000-03-28
Niebling, John F.
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
438159, 438303, 438305, H01L 2100
Patent
active
06043113&
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to semiconductor fabrication methods and in particular to a method of doping a compound semiconductor material. More specifically, the present invention relates to a method of forming a self-aligned thin film transistor (TFT).
BACKGROUND ART
Self-aligned field effect transistors (FETS) are known in the art. During the formation of transistors of this nature, ion implantation has been used to form the heavily doped source and drain regions of the transistor so that the edges of the source and drain regions line up with the edges of the gate electrode. This doping of the source and drain regions is of course necessary since these regions are unmodulated by the gate electrode. Since there is no overlap of the source and drain regions with the gate electrode, the parasitic capacitance of the transistor is greatly reduced as compared to conventional transistors having gate electrodes and source and drain regions that overlap.
Parasitic capacitance affects the switching speed of a transistor. Therefore, in environments requiring high speed switching, such as in driver circuits for active matrix liquid crystal displays (AMLCDs), it is desired to minimize the parasitic capacitance of transistors to increase their switching speed. Although ion implantation methodology has allowed self-aligned transistors which reduce parasitic capacitance to be fabricated, ion implantation is a high energy process. Accordingly, alternative methods of doping semiconductor material and fabricating self-aligned transistors which reduce energy requirements are desired.
Therefore, it is an object of the present invention to provide a novel method of doping compound semiconductor material and a novel method of forming a self-aligned thin film transistor.
DISCLOSURE OF THE INVENTION
According to one aspect of the present invention there is provided a method of doping a compound semiconductor material comprising the step of: a chemical reaction with the semiconductor material causing removal of a component of said semiconductor material thereby to change its electrical properties and dope said semiconductor material.
According to another aspect of the present invention there is provided a method of forming a self-aligned thin film transistor comprising the steps of: said surface and gate electrode with a gate insulating layer; said gate insulating layer, said channel layer being positioned over and extending beyond said gate electrode; overlying said gate electrode; semiconductor material causing removal of a component thereof, said reagent reacting with the portions of said channel layer not covered by said shield to form doped source and drain regions extending to the edges of said gate electrode and positioned on opposite sides of a channel; and and drain regions.
In yet another aspect of the present invention there is provided in a self-aligned thin film transistor fabrication method wherein a gate electrode is deposited on a substrate, said substrate and gate electrode are covered by a gate insulating layer, a channel and doped source and drain regions on opposite sides of said channel are deposited on said gate insulting layer and source and drain electrodes are formed and contact the respective source and drain region, the improvement comprising: said gate insulating layer; gate electrode; and to a reagent selected to yield a chemical reaction with said compound semiconductor material causing removal of a component of said semiconductor material thereby to change its electrical properties and define said doped source and drain regions.
In still yet another aspect of the present invention there is provided a method of forming a self-aligned thin film transistor, wherein a gate insulating layer covers a gate electrode and a surface of a glass substrate, said method comprising the steps of: said gate insulating layer, said channel layer being positioned over and extending beyond said gate electrode; overlying said gate electrode; semiconductor material causing removal of a component
REFERENCES:
patent: 4040073 (1977-08-01), Luo
patent: 5157000 (1992-10-01), Elkind et al.
G. D. Davis and N. E. Byer, "Surface stoichiometry changes induced by the hydrogenation of Hg.sub.0.72 Cd.sub.0.28 Te," Journal of Vacuum Science & Technology, A3(1), (Jan.Feb. 1985), pp. 203-205.
R. R. Daniels, et al., "Changes in the local chemical composition during the Hg.sub.1-x Cd.sub.x Te-A1 interface formation," Appl. Phys. Letts., 42(1), (Jan. 1983), pp. 50-52.
D. Ballutaud, et al., "Reactivity of III-V and II-VI semiconductors toward hydrogen: surface modification and evolution in air," Applied Surface Science, vol. 84, No. 2 (Feb. 1995), pp. 187-192.
Applied Physics Letters, vol. 62, No. 18, May 3, 1993, New York, YS, pp. 2254-2255, XP000565185 C.Debienne-Chouvy et al.
1294339 Ontario, Inc.
Lattin Christopher
Niebling John F.
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