Method of forming self-aligned contacts and local interconnects

Details Method of forming self-aligned contacts and local interconnects Method of forming self-aligned contacts and local interconnects

2009-07-20

2011-12-13

Wilczewski, Mary (Department: 2822)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S258000, C438S303000, C438S595000, C438S639000, C438S700000, C438S734000, C438S740000, C257SE21249, C257SE21577, C257SE21585

Reexamination Certificate

active

08076230

ABSTRACT:
A method for simultaneous formation of a self-aligned contact of a core region and a local interconnect of a peripheral region of an integrated circuit includes etching a cap dielectric layer to simultaneously form a hole in the core region and a trench in the peripheral region of the cap dielectric layer, etching a dielectric layer to simultaneously form a hole in the core region and a trench in the peripheral region of the dielectric layer of the dielectric layer, etching a liner layer simultaneously on a shoulder of sidewall spacers associated with the hole and with the trench of the dielectric layer without etching the liner layer at a bottom area of the hole and the trench, performing an oxygen flushing to remove polymer residues, and etching simultaneously through the liner layer that lines the bottom area of the hole and the trench.

REFERENCES:
patent: 5668065 (1997-09-01), Lin
patent: 6271087 (2001-08-01), Kinoshita et al.
patent: 6306713 (2001-10-01), Hu et al.
patent: 7094672 (2006-08-01), Chen et al.
patent: 2007/0004187 (2007-01-01), Wei

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