Method of forming self-aligned contacts and local interconnects

Details Method of forming self-aligned contacts and local interconnects Method of forming self-aligned contacts and local interconnects

2005-07-01

2009-08-18

Prenty, Mark (Department: 2822)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S597000

Reexamination Certificate

active

07575990

ABSTRACT:
A method of forming a plurality of self-aligned contacts of a core region and local interconnect openings of a peripheral region of a semiconductor device is disclosed. A plurality of gate-structures are formed on the core and peripheral regions of a semiconductor substrate. Sidewall spacers then are formed around the gate structures. A liner layer and a dielectric layer are sequentially formed on the semiconductor substrate. Then a photoresist pattern is formed to define a plurality of self-aligned contacts of said core region and local interconnect openings of the peripheral region, and the dielectric layer, liner layer and sidewall spacers are etched to form a plurality of self-aligned contacts of the core region and local interconnect contacts of the peripheral region. This is achieved by an etching step having a high selectivity with respect to the dielectric layer and sidewall spacers.

REFERENCES:
patent: 5668065 (1997-09-01), Lin
patent: 6271087 (2001-08-01), Kinoshita et al.
patent: 2007/0004187 (2007-01-01), Wei

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