Method of forming salicide

Details Method of forming salicide Method of forming salicide

2002-04-25

2004-02-24

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Forming schottky junction

Using platinum group metal

C438S563000, C438S592000, C438S659000, C257S340000, C257S570000, C257S384000, C257S386000, C257S388000

Reexamination Certificate

active

06696354

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to semiconductor manufacturing, and particularly to a method of forming a salicide without consuming the silicon in the substrate such that junction leakage occurs.
2. Description of the Related Art
In semiconductor technology, a Metal-Oxide-Semiconductor transistor comprises a gate and a source/drain. The gate comprising a metal layer and SiO
2
is deposited on a silicon-based substrate. Most of the metal has bad adhesion with SiO
2
. Thus, polysilicon with good adhesion is proposed to replace the metal layer. However, the resistance of polysilicon interconnections is so high that polysilicon is not appropriate as a conductive layer. One way to solve this problem is to form a metal salicide on the polysilicon to enhance the conductivity. As methods of fabricating semiconductor integrated circuits (IC) continually improve, the number of devices that may be introduced into a single semiconductor chip has increased, while the size of each device has decreased. Millions of devices may now be fabricated on a single chip. Therefore, the salicide process is widely applied to ensure shallow junction or ultra shallow junction.
FIGS. 1A-1F
are schematic cross-section illustrating steps for forming a salicide of the prior art. In
FIG. 1A
, a substrate
10
comprises a gate oxide layer
11
, a polysilicon gate
12
, a source/drain
14
, a spacer
20
, and a field oxide
22
. The substrate
10
is cleaned by HF solution, and a metal layer
30
is formed on the substrate
10
to cover the polysilicon gate
12
, the source/drain
14
, and the spacer
20
, as shown in
FIG. 1B. A
first rapid thermal process is performed at 650-700° C. in nitrogen atmosphere, and the metal salicide
31
is formed by reacting the portions of the metal in the metal layer
30
with the silicon in the gate
12
as well as in the source/drain
14
, as shown in FIG.
1
C. The portions of the metal in the metal layer
30
on the spacer
20
and the field oxide
22
remain the same without reacting. Then, a second thermal process is performed at about 800° C. in nitrogen atmosphere, and the phase of the metal salicide
31
is changed to a phase with lower resistance, as shown in FIG.
1
E. The salicide process of prior art is accomplished.
The silicon in the source/drain
14
consumes the metal salicide
31
during the salicide process. For example, the reaction follows the following rule when a cobalt salicide is formed: Co+Si→CoSi
2
The ratio of the thickness of Co:Si:CoSi
2
is 1:3.6:3.5. Silicon with about 360 Å thickness must be consumed to form a CoSi
2
with about 350 Å thickness. Therefore, 0.04 of the source/drain
14
is lost, and the problem of the junction leakage following occurs, as shown in FIG.
2
.
SUMMARY OF THE INVENTION
To solve above problem, it is an object of the present invention to provide a method of forming a salicide to excess consumption of silicon in the substrate.
The method comprises the following steps. First, a silicon-based substrate comprising a gate with a spacer on the side wall of the gate and a source/drain is provided. Next, a metal layer is formed according to the topography of the substrate to cover the gate, the spacer, and the source/drain. A first thermal treatment is performed to react the portions of the metal in the metal layer with the silicon in the gate and the source/drain to form a salicide. Then, the unreacted metal and the spacer are removed. An ion containing silicon is introduced into the source/drain as an extra silicon source for salicide. Finally, a second thermal treatment is performed.
In the preferred embodiment of the present invention, the silicon ion is introduced by ion implantation. The first and second thermal treatment are perferably performed by rapid thermal processes between about 600° C. and 800° C. Besides, the unreacted metal layer and the spacer are removed by etching as is well known.


REFERENCES:
patent: 5924001 (1999-07-01), Yang et al.
patent: 6284612 (2001-09-01), Wu

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