Method of forming S/D extension regions and pocket regions...

Details Method of forming S/D extension regions and pocket regions... Method of forming S/D extension regions and pocket regions...

2001-04-17

2003-02-11

Whitehead, Jr., Carl (Department: 2822)

Semiconductor device manufacturing: process

With measuring or testing

C438S301000, C438S303000, C438S289000, C438S514000

Reexamination Certificate

active

06518075

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device having a transistor with SD extension regions and pocket regions, and more particularly to a method of manufacturing a semiconductor device having a transistor whose gate length is 0.18 &mgr;m or less.
2. Description of the Related Art
Next-generation transistors whose gate length is 0.18 &mgr;m or less are of a structure having SD extension regions and pocket regions, as shown in
FIG. 1
of the accompanying drawings, for example, in order to increase an ON current for high-speed transistor operation and prevent a threshold voltage V
TH
from being lowered due to a known short channel effect.
The structure of an n-channel MOS (nMOS) transistor will be described below. A p-channel MOS (pMOS) transistor is basically of the same structure as such an n-channel MOS transistor except that a different impurity is injected.
As shown in
FIG. 1
, semiconductor substrate
1
has trenches of uniform depth filled with an oxide film (STI: Shallow Trench Isolation) as device separating regions
2
for separating transistors from each other. On semiconductor substrate
1
, there are deposited gate insulating film
3
comprising an oxide nitride film, gate electrode
4
comprising a polysilicon film with phosphorus (P) or arsenic (As) injected therein, and a pair of side walls
5
disposed on opposite sides of gate electrode
4
for introducing ions at different rates into semiconductor substrate
1
to form SD extension regions and source/drain regions.
Semiconductor substrate
1
has source/drain regions
6
with arsenic (As) diffused therein in the vicinity of the surface thereof between device separating regions
2
of STI and side walls
5
, and SD extension regions
7
disposed between ends of gate electrode
4
and ends of side walls
5
and containing an impurity (n type) at a density higher than source/drain regions
6
. Semiconductor substrate
1
also has pocket regions
8
disposed near ends of source/drain regions
6
(near a channel), and containing an impurity (p type) at a density higher than semiconductor substrate
1
or a well region.
SD extension regions
7
have their impurity density higher than source/drain regions
6
for reducing the parasitic resistance of source/drain ends near the channel to increase the ON current. Since SD extension regions
7
intensify the short channel effect, however, pocket regions
8
having their impurity density higher than semiconductor substrate
1
or the well region are included to increase the impurity density on both channel ends thereby to prevent the threshold voltage V
TH
from being lowered. As shown in
FIG. 1
, the length of gate electrode
4
in the direction across the channel is generally referred to as gate length L, and the length between SD extension regions
7
as effective channel length L
eff
.
A method of manufacturing a semiconductor device having the transistor shown in
FIG. 1
will be described below with reference to
FIGS. 2A through 2I
of the accompanying drawings.
FIGS. 2A through 2I
show successive steps of a typical fabrication process for transistors whose gate length is 0.13 &mgr;m.
First, STI is formed in semiconductor substrate
1
according to a known process, thus forming device separating regions
2
for separating transistors.
Then, photoresist film
11
is deposited on semiconductor substrate
1
in a region other than a region where a pMOS transistor is to be formed, by photolithography. Then, phosphorus (P) is injected into the region where the pMOS transistor is to be formed under the conditions of 350 KeV and 2×10
13
atms/cm
2
, for example, to form an n well region (not shown), and arsenic (As) is further injected under the conditions of 100 KeV and 6×10
12
atms/cm
2
to form a channel region (not shown) of the pMOS transistor (see FIG.
2
A).
Then, photoresist film
12
is deposited on semiconductor substrate
1
in a region other than a region where an nMOS transistor is to be formed, by photolithography. Then, boron (B) is injected into the region where the nMOS transistor is to be formed under the conditions of 150 KeV and 2×10
13
atms/cm
2
, for example, to form a p well region (not shown), and boron is further injected under the conditions of 30 KeV and 2×10
12
atms/cm
2
to form a channel region (not shown) of the nMOS transistor (see FIG.
2
B).
Then, the surface of semiconductor substrate
1
is thermally oxidized and nitrided in a mixed atmosphere of nitrogen (N
2
) and oxygen (O
2
), growing gate insulating films
3
to a thickness of about 2.6 nm. A polysilicon film having a thickness of about 150 nm, which serves as gate electrodes
4
, is deposited on gate insulating films
3
by CVD (Chemical Vapor Deposition). Thereafter, a photoresist film (not shown) is formed on the polysilicon film and patterned to a desired shape by photolithography. The polysilicon film is then etched away to form gate electrodes
4
(see FIG.
2
C).
Then, photoresist film
13
is deposited on semiconductor substrate
1
in the region other than the region where the nMOS transistor is to be formed, by photolithography. Then, arsenic (As) is injected vertically into the region where the nMOS transistor is to be formed under the conditions of 2 KeV and 5×10
14
atms/cm
2
, for example, to form SD extension regions
7
of the nMOS transistor, and boron fluoride (BF
2
) is further injected rotationally (at about 30° to the vertical direction) under the conditions of 30 KeV and 1.3×10
13
atms/cm
2
to form pocket regions
8
of the nMOS transistor (see FIG.
2
D).
Then, after the assembly is processed by an RTA (Rapid Thermal Anneal) process at 950° C. for 10 sec. in a nitrogen atmosphere to eliminate point defects caused by the injection of arsenic (As) and boron fluoride (BF
2
), photoresist film
14
is deposited on semiconductor substrate
1
in the region other than the region where the pMOS transistor is to be formed, by photolithography. Then, boron fluoride (BF
2
) is injected vertically into the region where the pMOS transistor is to be formed under the conditions of 2.5 KeV and 5×10
14
atms/cm
2
, for example, to form SD extension regions
7
of the pMOS transistor, and arsenic (As) is further injected rotationally (at about 30° to the vertical direction) under the conditions of 80 KeV and 1.5×10
13
atms/cm
2
to form pocket regions
8
of the pMOS transistor (see FIG.
2
E).
Then, an oxide film (TEOS-NSG) is grown to a thickness of about 70 nm on semiconductor substrate
1
in covering relation to gate electrodes
4
by a thermal CVD process, and then etched back by a dry etching process to form side walls
5
on both sides of gate electrodes
4
.
Then, photoresist film
15
is deposited on semiconductor substrate
1
in the region other than the region where the pMOS transistor is to be formed, by photolithography. Using the gate electrode
4
as a mask in the region where the pMOS transistor is to be formed, boron (B) is injected vertically under the conditions of 3 KeV and 5×10
15
atms/cm
2
, for example, to form source/drain regions
6
of the pMOS transistor. In this ion implantation process, boron is also injected into gate electrode (polysilicon)
4
of the pMOS transistor (see FIG.
2
F).
Then, photoresist film
16
is deposited on semiconductor substrate
1
in the region other than the region where the nMOS transistor is to be formed, by photolithography. Using the gate electrode
4
as a mask in the region where the nMOS transistor is to be formed, arsenic is injected vertically under the conditions of 30 KeV and 6×10
15
atms/cm
2
, for example, to form source/drain regions
6
of the pMOS transistor. In this ion implantation process, arsenic is also injected into gate electrode (polysilicon)
4
of the nMOS transistor (see FIG.
2
G).
The dopants injected into source/drain regions
6
are activated by the RTA process at 1000° C. for 10 sec. in a nitrogen atmosphere. Thereafter, a f

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