Method of forming pre-metal dielectric layer

Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region

Reexamination Certificate

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C438S663000, C438S680000, C438S692000, C257SE21170, C257SE21248, C257SE21304, C257SE21334

Reexamination Certificate

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11126900

ABSTRACT:
A method of forming a pre-metal dielectric (PMD) layer is disclosed. In the method, after a nitride liner layer is formed on a substrate having a transistor, a USG layer is deposited thereon and then planarized. Next, ion implantation and annealing are performed for gettering, first in a gate region and then in a non-gate region of the USG layer. The USG layer is generally free from plasma damage and has a good gap-fill capability. Further, ion implantation and annealing after deposition of the USG layer may enhance a gap-fill capability, a gettering capability, and electrical properties of a transistor.

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Inoue Akira; Manufacture of Semiconductor Device; Patent Abstracts of Japan; Aug. 4, 2000; Publication No. 2000216245 A; Japanese Patent Office; Japan.

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